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preliminary CY15B104QSN cy15v104qsn excelon?-ultra 4-mbit (512k 8) quad spi f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-18293 rev. *e revised march 1, 2018 excelon?-ultra 4-mbit (512k 8) quad spi f-ram features 4-mbit ferroelectric random access memory (f-ram) logically organized as 512k 8 ? virtually unlimited endurance of 100 trillion (10 14 ) read/write cycles ? 151-year data retention (see data retention and endurance on page 75 ) ? nodelay? writes ? advanced high-reliability ferroelectric process single and multi i/o serial peripheral interface (spi) ? serial bus interface spi protocols ? supports spi mode 0 (0, 0) a nd mode 3 (1, 1) for all sdr mode transfers ? extended i/o spi protocols ? dual spi (dpi) protocols ? quad spi (qpi) protocols spi clock frequency ? up to 108-mhz frequency spi single data rate (sdr) execute-in-place (xip) write protection, data secu rity, and data integrity hardware protection usin g the write protect (wp ) pin software block protection embedded error correction code (ecc) and cyclic redundancy check (crc) for enhanced data integrity ? ecc detects and corrects 1-bit error. if a 2-bit error occurs, it does not correct but reports through the ecc status register ? crc detects any accidenta l change to raw data extended electronic signatures ? device id includes manufac turer id and product id ? unique id ? user writable serial number dedicated 256-byte special sector f-ram ? dedicated special sector write and read ? content can survive up to th ree standard reflow cycles low-power consumption at high speed ? 10 ma (typ) active current for 108 mhz spi sdr ? 16 ma (typ) active curren t for 108 mhz qspi sdr ? 102 a (typ) standby current ? 0.70 a (typ) deep pow er down mode current ? 0.1 a (typ) hiber nate mode current low-voltage operation: ? cy15v104qsn: v dd = 1.71 v to 1.89 v ? CY15B104QSN: v dd = 1.8 v to 3.6 v operating temperatur e: C40 c to +85 c packages ? 8-pin small outline integr ated circuit (soic) package ? 8-pin grid-array quad flat no-lead (gqfn) package restriction of haz ardous substances (rohs) compliant functional description the excelon-ultra cy15x104qsn i s a high-performance, 4-mbit nonvolatile memory employin g an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads a nd writes similar to a ram. it provides reliable data retention for 151 years while eliminating the complexities, overhead, an d system-level reliability proble ms caused by serial flash and other nonvolatile memories. unlike serial flash, the cy15x10 4qsn performs wr ite operations at bus speed. no write delays ar e incurred. data is written to the memory array immediately af ter each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product off ers substantial write endurance compared to other nonvolatile memories. the cy15x104qsn is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom. these capabilities mak e the cy15x104q sn ideal for nonvolatile memory applications, requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial contro ls where the long write t ime of serial flash can cause data loss. the cy15x104qsn combines a 4-mbit f-ram with the high-speed quad spi (qpi) single data rate (sdr) interface which enhances the nonvolatile write capability of f-ram technology. the device incorporates a read-only device id and unique id features which allow the spi bus master to determine the manufacturer, product density, product revision and unique id for each part. the device is also offered with a unique seri al number that is read-only and can be used to identify a board or a system. the device supports on-die ecc logic which can detect and correct 1-bit error in every 8-b yte data unit. the device also extends capability to report 2-bit error in unit data. the cy15x104qsn also supports the cyclic redundancy check (crc) feature which can be used to check the data integrity of the stored data in the memory array. the device specifications are guaranteed over industrial temperature range of C40 c to +85 c.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 2 of 90 logic block diagram si (i/o0) so (i/o1) wp (i/o2) reset (i/o3) cs sck f-ram & nonvolatile registers access control 512k x 8 f-ram array 256-byte special sector f-ram status registers configuration registers instruction decoder spi control logic reset logic write protect power control block v dd device id serial number registers unique id
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 3 of 90 contents pinout ........................................................ ........................ 4 pin definitions ............................................... ................... 5 functional overview ........................................... ............. 6 memory architecture ......... .................................. ........ 6 serial peripheral interface (spi) bus ......................... .6 terms used in spi protocol . ................................... ..... 7 spi modes ..................................................... .............. 9 power-up to first access ...................................... .... 10 cy15x104qsn registers ....... .............. ........... ......... ...... 11 status registers .............................................. .......... 11 configuration registers ....................................... ...... 14 functional description ........................................ ........... 20 command structure ............................................. ..... 20 maximum ratings ............................................... ............ 73 operating range ............................................... .............. 73 dc electrical characteristics ................................. ....... 73 data retention and endurance .................................. ... 75 capacitance ................................................... ................. 75 thermal resistance ............................................ ............ 75 ac test conditions ............................................ ............ 76 sdr ac switching characteristics .............................. .77 write protect (wp ) timing parameters ......................... 79 reset (reset ) timing parameters ............................... 79 power cycle timing ............................................ ........... 80 ordering information .......................................... ............ 81 ordering code definitions ..................................... .... 81 package diagrams .............................................. ............ 82 acronyms ...................................................... .................. 84 document conventions .......................................... ....... 84 units of measure .............................................. ......... 84 document history page ......................................... ........ 85 sales, solutions, and legal information ...................... 9 0 worldwide sales and design s upport ......... .............. 90 products ...................................................... .............. 90 psoc? solutions ............................................... ....... 90 cypress developer community . ................................ 90 technical support ........... .................................. ........ 90
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 4 of 90 pinout figure 1. 8-pin soic pinout figure 2. 8-pin gqfn pinout si/(i/o0) reset/(i/o3) sck so/(i/o1) cs wp/(i/o2) v ss v dd top view (not to scale) 8 7 6 5 1 2 3 4 si/(i/o0) reset/(i/o3) sck so/(i/o1) cs wp/(i/o2) v ss v dd top view (not to scale) 8 7 6 5 1 2 3 4
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 5 of 90 pin definitions pin name i/o type description cs input chip select. this active low input activates the device. when high, the dev ice enters low-power standby mode, ignores other inputs, and the output is tristated . when low, the device internally activates the sck signal. a falling edge on cs must occur before a new opcode is issued. sck input serial clock. all i/o activity is synchronized to the serial clock. inputs ar e latched on the rising edge and outputs occur on the f alling edge. because the device is synchronous, the clock frequency may be any value betwe en 0 and 108 mhz and may be int errupted at any time. si / (i/o0) input serial input. all data is input to the device on this pin. the pin is sample d on the rising edge of sck and is ignored at o ther times. it should always be driven t o a valid logic level to meet idd specifications. input/output i/o0: when the part is either in dual mode or quad mode, the si pin becomes input/output (i/o0) pin and acts as input during command and address cycles and out put during t he data output cycle. so / (i/o1) output serial output. this is the data output pin. it is driven durin g a read and re mains tristated at all other times including when reset is low. data transitions are driven on the falling edge of the serial clock. input/output i/o1: when the part is either in dual mode or quad mode, the so pin becomes input/output (i/o1) pin and acts as input during command and address cycles and out put during t he data output cycle. wp / (i/o2) input write protect. this active low pin prevents wr ite operation to t he status and configuration registers when srwd bit (sr1[7]) is set to 1. a complete expl anation of write protection is provided in status register 1 ( sr1) on page 11 . this pin has an internal weak pull up resistor which keeps this pin high if lef t floating (not connected on th e board). this pin can also be tied to v dd if not used. input/output i/o2: when the part is i n quad mode, the wp pin becomes input/output (i/o2) pin and acts as input during command and address cycles and outpu t during the d ata output cycle. reset / (i/o3) input hardware reset pin. this active low pin resets the device. when reset is low, the device will self-initialize and will return to either standby state or active state depending on cs high or low status after the reset input is released to high. this pin has an inte rnal weak pull up resistor which keeps this pin hi gh if left floating (not connec ted on the board). this pin can also be tied to v dd if not us ed. reset / (i/o3) behavior is described in table 16 on page 17 . input/output i/o3: when the part i s in quad m ode, the reset pin becomes input/output (i/o3) pin and acts as input during comma nd and address cycles a nd output during th e data output cycle. the internal pull-up resistor on this pin gets disabled when config ured as i/o2. v ss power supply ground for the devic e. must be connected to the gro und of the system. v dd power supply power supply input to the device.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 6 of 90 functional overview the cy15x104qsn is a serial f-ram memory. the memory array is logically organized as 524,288 8 bits and is accesse d using an industry-standard serial peripheral interface (spi) bu s. the functional operation of the f-ram is similar to single spi eeprom or single/dual/quad spi flash. the key differences between the cy15x104qsn and a serial flash with the same pinout is the f-rams superior write performance, high endurance, and lower power consumption. memory architecture when accessing the cy15x104qsn, the user addresses 512k locations of eight data bits each. these eight data bits are sh ifted in or out serially either on single, dual, or quad i/os. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an opcod e, and a three-byte (24-bit) address. however, since cy15x104qsn requires only 19 bits to address its entire 512k byte locations, the upper 5 bits of the most significant addres s byte are dont care values. the 19-bit address uniquely identifies each data byte locat ion in the 512k memory array. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition before initiating a new command. this is explained in more detail in the functional description on page 20 . serial peripheral in terface (spi) bus the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on the sp i bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on th e rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. the cs must go inactive after an operat ion is complete and before a ne w opcode can be issued. the cy15x104qsn is an spi slave device and operates at speeds up to 108 mhz in single data rate (sdr) mode. this high-speed serial bus provides high-performance serial communication to an spi master. the cy15x104qsn supports four different spi interface/protocol options: single channel s pi, extended spi, dual spi, quad spi. refer to ta b l e 1 for i/o signaling details during opcode, address, and data phase in various spi modes discussed above. table 1. spi modes and signal details interface single channel spi extended spi [1] multi-channel spi dual data quad data dual i/o quad i/o dpi qpi signals cs , sck, si, so cs , sck, i/o0, i/o1 cs , sck, i/o0, i/o1, i/o2, i/o3 cs , sck, i/o0, i/o1 cs , sck, i/o0, i/o1, i/o2, i/o3 cs , sck, i/o0, i/o1 cs , sck, i/o0, i/o1, i/o2, i/o3 opcode si i/o0 i/o0 i/o0 i/o0 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 address si i/o0 i/o0 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 data si/so i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 note 1. there is no user setting for the extended spi modes. device a lways starts with spi mode and then changes to the respective e xtended spi mode based on the opcode received.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 7 of 90 single channel spi the single channel spi is a four-pin interface with chip select (cs ), serial input (si), serial output (so), and serial clock (sck) pins. after cs is activated, the first byte transferred from the bus master is the opcode. following the opcode, any addresses and data are then transferred. the cs must go high (inactive) after an operation is complete and before a new opcode can be issued. this mode uses si and so pins for input and output respectively. opcode and address is transferred by the master on the si line, while data is read by the master on so. extended spi the cy15x104qsn has the capability to reconfigure the standard spi pins to work in dual or quad i/o modes called extended spi modes. the extended spi mode provides: dual data, dual input/output (i/o), quad data, and quad input/output (i/o) modes. the cs going high after extended spi command or device reset (either por or hardware/software reset) brings the device back to the single channel spi mode. extended spi mode has the following i/o configurations: when the part is in dual output or dual i/o mode, the si pin an d so pin become i/o0 pin and i/o1 pin respectively. when the part is in quad output or quad i/o mode, the si pin, so pin, wp pin, and reset pin become i/o0 pin, i/o1 pin, i/o2 pin, i/o3 pin respectively. dual or quad data commands and addresses are sent to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on i/ o0 and i/o1 or four bit (nibble ) groups on i/o0, i/o1, i/o2, and i/o3. dual or quad input/ output (i/o) commands are sent to the memory only on si signal while an address is sent from the host as bit pairs on i/o0 and i/o1 or, four bit (nibble) groups on i/o0, i/o1, i/o2, and i/o3 respect ively. data is returned to th e host similarly as bit pairs on i/o0 and i/o1 or, four bit (nibb le) groups on i/o0, i/o1, i/o2, and i/o3. dual spi (dpi) the cy15x104qsn multichannel dpi mode is enabled by writing 1 at bit 4 of configuration register 2 (cr2) , cr2[4] = 1. since configuration register 2 (cr2) is nonvolatile, user setting will survive power and reset cycles . therefore, once the dual s pi mode is set, it remains in dual spi mode until the bus master clears by writing bit 0 in cr2[4]. when the part is in dual spi mode, the si pin and so pin become i/o0 pin and i/o1 pin respectively. command, address, and data bits are sent to the memory from the host as bit pairs on i/o0 and i/o1. data bits are returned to the ho st similarly as bit pairs on i/o0 and i/o1. quad spi (qpi) the cy15x104qsn multichannel qpi mode is enabled by writing 1 at bit 6 of configuration register 2 (cr2) , cr2[6] = 1. since configuration register 2 (cr2) is nonvolatile, user setting will survive power and reset cy cles. therefore, once the quad spi mode is set, it remains in quad spi mode until the bus master clears by writing bit '0' in cr2[6]. when the part is in quad spi mode, the si pin, so pin, wp pin, and reset pins become i/o0 pin, i/o1 pin, i/o2 pin, i/o3 pin respectively. command, address, and data bits are sent to the memory from the host as four bit (nibble) groups on i/o0, i/o1, i/o2, and i/o3. data bits are returned to the host simila rly as four bit (nibble) groups on i/o0, i/o1, i/o2, and i/o3. terms used in spi protocol the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on the spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of the slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchroni zed with this clock. spi slave the spi slave device is activated by the master through the chi p select line. a slave device gets the sck as an input from the s pi master and all the communicat ion is synchronized with this clock. an spi slave never initiates a communication on the spi bus and acts only on the inst ruction from the master. the cy15x104qsn operates as an spi slave and may share the spi bus with other spi slave devices. chip select (cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial out put pin (so) remains in a high-impedance state. note: a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active cs high to low transition.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 8 of 90 serial clock (sck) the serial clock is generated by the spi master and the commu- nication is synchronized with this clock after cs goes low. the cy15x104qsn enables spi modes 0 and 3 for data communication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefore, the first rising edge of sck signifies the arrival of the first most significant bit (msb) o f an spi instruction on the si pin. further, all data inputs and out puts are synchronized with sck. data transmission (si/so) the spi data bus consists of two lines, si and so, for serial d ata communication. si is also refe rred to as master-out-slave-in (mosi) and so is referred to a s master-in-slave-out (miso). the master issues instructions to the slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the cy15x104qsn has two separat e pins for si and so, which can be connected with the master as shown in figure 3 . when in dual or quad i/o modes, thes e pins are configured as i/o pin s. figure 4 shows such a system inter face with a qspi port. figure 3. system configuration with spi port figure 4. system configuration with qspi port most signific ant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). th is is valid for both address and data transmission. the 4-mbit serial f-ram require s a 3-byte address for any read or write operation. because the address is only 19 bits, the five bits, which are fed in are ignored by the device. although these five bits are dont care, cypress recommends that these bits be set to 0s to enable seamless transition to higher memor y densities. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operati on. cy15x104qsn uses the standard opcodes (refer to table 25 on page 20 ) for memory accesses. invalid opcode if a reserved opcode is received, the opcode may internally trigger unintended ope ration and start drivi ng the i/o pin(s) w ith a non-deterministic data output . hence, all opcodes under the reserved category should be avoided to transmit over si pin when cy15x104qsn chip select cs is low. instruction instruction is the combinatio n of the opcode, address, mode and/or dummy bytes/cycles used to access the memory and registers mode bits the mode byte is applicable for all write and read commands tha t support execute-in-place (xip). the xip is a method of executing the program (code) di rectly from an external memory rather than copying or shadowing the code into ram. when the xip is set for a write or read command, the device stays in xip mode after the command cycle is terminated (cs toggles high) so that the subsequent command cycle with cs low directly starts with the address phase (opcode phase is skipped). when in xip, the device executes the same operation as in previous cycle. to initiate a new operati on while in xip, for example to switch from memory write to me mory read or vice versa, the device should first exit the xi p for the current command cycle and initiate the next command cycle with opcode phase. opcodes with the mode phase o nly support the xip. see table 25 on page 20 for the list of opcodes that require mode phase. following the opcode and 3-byte address cycles, the mode byte 0xax (x dont care bits) or 0xa5 (depending on the opcode) transmitted during the mode phase keeps the device in xip for the next command cycle. the xip must be set during every command cycle to remain in xip for the next command cycle. any other value than 0xax or 0xa5 (!0xax or !0xa5) transmitted during the mode phase will exit the xip for the current operati on. in this case, the next command cy cle must always start with the opcode phase to start the same operation or a new operation. depending upon the spi mode and the interface type, the number of clocks to transmit th e mode byte will vary from two clocks (qpi, sdr ) to eight clocks (spi, sdr). spi hostcontroller or spi master sck mosi miso cs1 cs2 gpio1 gpio 2 sck (i/o0) si (i/o1) so reset (i/o3) wp (i/o2) cy15x104qsn cs sck (i/o0) si (i/o1) so reset (i/o3) wp (i/o2) cy15x104qsn cs optional connection; leave floating if not used qspi hostcontroller or qspi master sck i/o0 i/o1 cs1 cs2 i/o2 i/o3 sck (i/o0) si (i/o1) so reset (i/o3) wp (i/o2) cy15x104qsn cs sck (i/o0) si (i/o1) so reset (i/o3) wp (i/o2) cy15x104qsn cs
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 9 of 90 wait states or dummy cycles the wait states, also called dummy cycles, are appended after the address bits and mode bits (if applicable). the number of w ait state cycles are programmable through configuration register 1 (cr1) and configuration register 2 (cr2) for both memory and registers reads respectively. a v alid data is driven on the out put bus only after specific numbe r of dummy cycles are elapsed following memory and register read commands that support wait state. a dummy cycle is a full clock cycle irrespective of the spi modes and data rates. the status of i/os are dont care during dummy cycle. spi modes cy15x104q may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) the device detects the spi mode from the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. the two spi modes are shown in figure 5 and figure 6 . the status of the clock sck when the bus master is not transferring data i s: sck remains at 0 for mode 0 sck remains at 1 for mode 3 spi mode 0 and spi mode 3 are supported for all sdr mode commands. figure 5. spi mode 0 figure 6. spi mode 3 single data rate (sdr) the input data bits (includes instruction, address, and data) a re always latched in on the rising edge of sck starting from the f irst rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggle s is considered. the output data is available on the falling edge of sck. 012345 67 0 1 2 3 4 5 6 7 cs sck si 012345 67 0 1 2 3 4 5 6 7 sck si cs
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 10 of 90 power-up to first access when the cy15x104qsn power supply (v dd ) falls below v dd (low), the power-up cycle starts. cy15x104qsn waits for the vdd power supply to rise above the minimum v dd (min), after which the device stars its internal boot-up sequence. the boot-up sequence for cy15x104qsn includes internal power-on-reset (por) followed by loading the internal device configuration and trim registers as well as setting the user accessible registers. all user accessible registers (status and configuration, mode, id, ecc, and crc) are set to their default values after a successful boot-up cycle. table 2 shows the status of each register of cy15x104qsn after a successful power-up (or por) sequence. cy15x104qsn ignores all instru ctions until a time delay of t pu has elapsed after the moment v dd rises above v dd (min). no instruction should be sent to the device until the end of t pu . after the t pu , if cs is high, the device enters standby mode and draws standby current (i sb ). the device enters deep power-down mode after t pu if the deep power-down mode upon por (dpdpor) in configuration register 4 (cr4) is set to 1 (cr4 [2] = 1). the wip bit of status register 1 (sr1[0]) cannot be used to pol l the device readiness after the por event because device is stil l not accessible for executing any command including rdsr1 until the t pu time is over. however, if the wip status remains high even after t pu time, indicates device didnt boot up correctly (boot error). once the boot error occurs, the device enters the following default states: the interface mode is s et to single spi (sdr) io3r bit of cr2 (cr2[5]) is in ternally set 1 to enable the hardware reset (reset ) on io3 register laten cy is set to th ree-clock cycl e (max value) output impedance is set to 45 ohm only rdsr1 and rdar commands are allowed (in spi sdr mode only) to read the sr1. a ll other command s will remain disabled and will return u ndefined data if executed. reading the sr1 returns 0x61 as boot error signature cy15x104qsn will require power cycle or hardware reset to restart the boot-up again. the above default settings will be replaced with actual user configurations after a successful boot-up. table 2. cy15x104qsn registers status after por function register type cy15x104qsn registers status after por device status status register 1 (sr1) default to corresponding no nvolatile bits status register 2 (sr2) 0x00 device configuration [2] configuration register 1 (cr1) default to corresponding nonvolat ile bits configuration register 2 (cr2) default to corresponding nonvolat ile bits configuration register 4 (cr4) default to corresponding nonvolat ile bits configuration register 5 (cr5) default to corresponding nonvolat ile bits identification identification register default to corresponding nonvolatile bits (factory set) unique identification register de fault to corresponding nonvolat ile bits (factory set) serial number register default to corresponding nonvolatile bits (factory set to 0x0000000000000000) error correction ecc s tatus register 0x00 ecc count register 0x0000 ecc address trap register 0x00000000 cyclic redundancy check crc register 0x00000000 note 2. configuration register 3 (cr3) is reserved for future use.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 11 of 90 cy15x104qsn registers cy15x104qsn supports various status and configuration registers for device status updat e and configuration settings. cy15x104qsn registers and their access details are discussed in the follow on sections. status registers the cy15x104qsn supports two status registers C status register 1 (sr1) and status regi ster 2 (sr2). the sr1 provides configuration options for vari ous controls and status in the pa rt. the sr2 is a read only status register and provides status of t he ecc suspend/abort. details on st atus registers are provided in the following sections. status register 1 (sr1) the status register 1 as shown in table 3 contains both status and control bits. the sr1 is a nonvolatile register and is accessible by the wrar comma nd for write operations and the rdsr1 or the rdar command for read operations. the sr1 access details are provided in register access commands on page 24 . the default state shown after each bit, in parenthesis in table 3 is the factory set value. status register protect (srwd) sr1 [7] this bit enables write protect for the status and configuration registers when this bit is set t o 1 and the write protect (wp ) input is driven low. in this mode, any instruction that changes the status registers or configuratio n registers content is ignored, effectively locking the state of the device. if the srwd is set to 0, irrespective of the wp status (low or high), status and configuration registers write pr otection remains disabled. refe r to table 7 on page 12 for the memory and status register protection options. table 3. status register 1 (sr1) sr1[7] sr1[6] sr1[5] sr1[4] sr1[3] sr1[2] sr1[1] sr1[0] srwd (0) rfu (0) tbprot (0) bp2 (0) bp1 (0) bp0 (0) wel (0) wip (0) table 4. status register 1 (sr1) details bit bit name bit function type read/write description sr1[7] srwd status register write disable nv r/w 1 = locks state of status & configuration r egisters when wp is low 0 = no register protection irre spective of the status of wp pin sr1[6] rfu reserved (0) reserved for future use sr1[5] tbprot top/bottom relative protection nv r/w 1 = protection star ts at memory array bottom 0 = protection starts at memory array top sr1[4] bp2 block protect bit nv r/w pr otects the selected address ra nge of memory array sr1[3] bp1 nv sr1[2] bp0 nv sr1[1] wel write enable latch v r wel indicates if the device is wri te enabled. this bit defaults to 0 (disabled) on power-up. wel = 1 --> write enabled wel = 0 --> write disabled sr1[0] wip work in progress v r 1 = device busy 0 = device ready nv - nonvolatile; v - volatile
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 12 of 90 top or bottom protection (tbprot) sr1 [5] this bit defines the operation of the block protection bits bp2 , bp1, and bp0. this bit controls the starting point of the mem ory array (from top or bottom) memory that gets protected by the block pr otection bits. block protection (bp2, b p1 and bp0) sr1 [4:2] these bits define the memory a rray to be software-protected against memory write commands. when one or more of the bp bits is set to 1, the respective memory address is protected from write. the block protect bits ( bp2, bp1, and bp0) in combinatio n with the tbprot bit can be used to protect an address range of the memory array. the size of the range is determined by the value of the bp bits and the upper or lower starting point of t he range which is selected by the tbprot. table 5 and ta b l e 6 show cy15x104qsn protected address range for bp[2:0] bits setting. write enable latch (wel) sr1 [1] the wel bit must be set to 1 to enable write operations to memory array or registers, as shown in ta b l e 7 . this bit is set to 1 only by executing the writ e enable (wren) command. the wel bit (sr1[1]) automatically clears to 0 on the rising edge of cs following opcodes including: wrdi (04h), sswr (42h), wrar (71h), and wrsn (c2h). the wel bit (sr1[1]) doesnt clear to 0 on the rising edge of cs following memory write opcodes. the wel bit is volatile and returns to its default 0 state after por and all reset events. table 5. start of protect ion from top (tbprot = 0) status register content protected fraction of memory array protected address range bp2 bp1 bp0 0 0 0 none none 0 0 1 upper 1/64 th of memory array 0x07e000C0x07ffff 0 1 0 upper 1/32 nd of memory array 0x07c000C0x07ffff 0 1 1 upper 1/16 th of memory array 0x078000C0x07ffff 1 0 0 upper 1/8 th of memory array 0x070000C0x07ffff 1 0 1 upper 1/4 th of memory array 0x060000C0x07ffff 1 1 0 upper half of memory array 0x040000C0x07ffff 1 1 1 full memory 0x000000C0x07ffff table 6. start of protectio n from bottom (tbprot = 1) status register content protected fraction of memory array protected address range bp2 bp1 bp0 0 0 0 none none 0 0 1 lower 1/64 th of memory array 0x000000C0x001fff 0 1 0 lower 1/32 nd of memory array 0x000000C0x003fff 0 1 1 lower 1/16 th of memory array 0x000000C0x007fff 1 0 0 lower 1/8 th of memory array 0x000000C0x00ffff 1 0 1 lower 1/4 th of memory array 0x000000C0x01ffff 1 1 0 lower half of memory array 0x000000C0x03ffff 1 1 1 full memory 0x000000C0x07ffff table 7. write protection srwd wp wel protected blocks unprotected blocks status and configu ration registers [3] x x 0 protected protected protected 0 x 1 protected writable writable 1 0 1 protected writable protected 1 1 1 protected writable writable note 3. all bits except read only and reserved bits.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 13 of 90 work-in-progress (wip) sr1 [0] this is a read-only bit and indicates device ready or busy stat us during normal operation. the cy15x104qsn sets this bit to 1 while executing the crc calculat ion. no other command (s) and event (s) set the wip to 1 in cy15x104qsn. when wip is 1, the cy15x104qsn can execute only read status (rdsr1/rdsr2), read any register (rdar), crc suspend (epcs), and software reset (rsten followed by rst) commands. other commands will be ignored while wip is1. the wip bit cant be used to poll the device ready status during po wer up or reset cycles. this bit is volatile and returns to its def ault state after por and all reset events. status register 2 (sr2) status register 2, as shown in table 8 , provides device status on crc operations. the sr2 is a read only volatile register and is accessible by rdsr2 or rdar commands for read opera- tions. the sr2 access details are provided in register access commands on page 24 . the default state shown after each bit in table 8 is the factory set value. crc suspend (crcs) sr2 [4] this bit is used to determine when the device is in crc suspend mode. when device is in crc suspend mode, after crc suspend command (epcs), this bit is set to 1 to indicate the crc suspend status. crc resume (epcr) command clears crcs bit to 0, indicates dev ice exited the crc suspend mode. this is a read only bit. this bit also gets cleared after reset s (por, hardware, and software). crc abort (crca) sr2 [3] this bit indicates whether the crc calculation operation is aborted. the crc calculation is aborted when end address and start address criteria (ea < sa + 3), which is ending address should be at least 32-bit aligned word higher than the starting address, doesnt meet. this bits gets clears when subsequent crc calculation starts successfully. this bit also gets cleared after reset (por, hw, sw). table 8. status register 2 (sr2) sr2[7] sr2[6] sr2[5] sr2[4] sr2[3] sr2[2] sr2[1] sr2[0] rfu (0) rfu (0) rfu (0) crcs (0) crca (0) rfu (0) rfu (0) rfu (0) table 9. status register 2 (sr2) details bit bit name bit function type read/write description sr2[7] rfu reserved (0) reserved for future use sr2[6] rfu reserved (0) reserved for future use sr2[5] rfu reserved (0) reserved for future use sr2[4] crcs crc suspend v r 1 = in crc suspend mode 0 = not in crc suspend mode sr2[3] crca crc abort v r 1 = crc command aborted 0 = crc command not aborted sr2[2] rfu reserved (0) reserved for future use sr2[1] rfu reserved (0) reserved for future use sr2[0] rfu reserved (0) reserved for future use v - volatile
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 14 of 90 configuration registers the cy15x104qsn supports four configuration registers cr1, cr2, cr4, and cr5 to configure various controls in the part. details on configuration registers are provided in the followin g sections. configuration register 1 (cr1) configuration register 1, as shown in ta b l e 1 0 , controls the interface and data protection functions. the cr1 is a nonvolati le register and is accessible by the wrar command for write and the rdcr1 or the rdar command for read operations. the cr1 access details are provided in register access commands on page 24 . the default state shown after each bit in table 10 is the factory set value. memory latency code (mlc) cr1 [7:4] these four bits control the lat ency (dummy cycle) delay in all variable latency memory read instructions. it enables the user to adjust the memory read latency during normal operation to optimize the latency for different instructions at different operating frequencies. dummy cycles are full clock cycles on sck irrespective of the spi modes and data rates. some read opcodes support dummy cycles following address cycles. these dummy cycles provid e additional l atency that is needed to complete the initial read access of the memory array before data can be returned to the host system. as the spi cloc k (sck) frequency increase, number of dummy cycles need to increase to meet the latency. ta b l e 1 2 to table 13 on page 15 show the max spi clock frequency versus clock latency for each opcodes that support dummy cycles. the host controller can determine to optimize the timing by setting individual lat ency cycle for each opcode or c an set the worst case latency code which meets the latency requirement of all opcodes for a desired operating frequency. the latency code values for a higher frequency will work at all lower frequencies. the format (cmd, add, data) in the table header represents the transmission of these bytes over number of i/os in differen t spi modes. for example: (2, 2, 2) represents all command (cmd), address (addr) , and data (data) bytes are transmitted over two i/os (i/o0 and i/o1) in dpi mode. similarly, (1, 2, 2) represents cmd byte is transmitted over a single i/o (i/o0), wh ile addr and data bytes are transmitted over two i/os (i/o0, i/o1) in dual i/o mode. (1, 1, 4) represents cmd and addr bytes are transmitted over a single i/o (i /o0), while data bytes are tran s- mitted over four i/os (i/o0, i/o1 , i/o2, i/o3) in quad data mod e. mode represents number of clock cycles required in various spi interface modes to transmit the mode byte after address bits. since mode bits are transmitted after the address cycles, clock cycles required to transmit mode b its are internally added to t he latency calculation. table 10. configuration register 1 (cr1) cr1[7] cr1[6] cr1[5] cr1[4] cr1[3] cr1[2] cr1[1] cr1[0] mlc3 (0) mlc2 (0) mlc1 (0) mlc 0 (0) rfu (0) rfu (0) quad (0) rfu (0) table 11. configuration register 1 (cr1) details bit bit name bit function type read/write description cr1[7] mlc3 memory latency code nv r/w selects number of m emory read latency cycles 0 to 15 latency (dummy) cycles following read address or continuous mode bits cr1[6] mlc2 nv cr1[5] mlc1 nv cr1[4] mlc0 nv cr1[3] rfu reserved (0) res erved for future use cr1[2] rfu reserved (0) res erved for future use cr1[1] quad quad nv r/w 1 = quad 0 = dual or serial cr1[0] rfu reserved (0) res erved for future use
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 15 of 90 table 12. latency (dummy) cycles for memory read commands - wi th xip mode (sdr) latency (dummy) cycles - decimal spi (sdr) dpi (sdr) qpi (sdr) dual data (sdr) dual i/o (sdr) quad data (sdr) quad i/o (sdr) fast_read fast_read fast_read, qior dor dior qor qior (1, 1, 1) (2, 2, 2) (4, 4, 4) (1, 1, 2) (1, 2, 2) (1, 1, 4) (1, 4, 4) mode = 8 mode = 4 mode = 2 mode = 8 mode = 4 mode = 8 mode = 2 0 108 mhz 60 mhz [4] 15 mhz [4] 108 mhz 60 mhz [4] 108 mhz 15 mhz [4] 1 108 mhz 80 mhz [4] 30 mhz [4] 108 mhz 80 mhz [4] 108 mhz 30 mhz [4] 2 108 mhz 100 mhz [4] 50 mhz [4] 108 mhz 100 mhz [4] 108 mhz 50 mhz [4] 3 108 mhz 108 mhz 60 mhz [4] 108 mhz 108 mhz 108 mhz 60 mhz [4] 4 108 mhz 108 mhz 80 mhz [4] 108 mhz 108 mhz 108 mhz 80 mhz [4] 5 108 mhz 108 mhz 100 mhz [4] 108 mhz 108 mhz 108 mhz 100 mhz [4] 6C15 108 mhz 108 mhz 108 mhz 108 m hz 108 mhz 108 mhz 108 mhz table 13. latency (dummy) cycles for memory read commands - wi thout xip mode latency (dummy) cycles - decimal spi (sdr) dpi (sdr) qpi (sdr) read, eccrd, ssrd (1, 1, 1) (2, 2, 2) (4, 4, 4) mode = na mode = na mode = na 0 50 mhz [4] na na 1 60 mhz [4] na na 2 80 mhz [4] 30 mhz [4] 15 mhz [4] 3 100 mhz [4] 50 mhz [4] 30 mhz [4] 4 108 mhz 60 mhz [4] 50 mhz [4] 5 108 mhz 80 mhz [4] 60 mhz [4] 6 108 mhz 100 mhz [4] 80 mhz [4] 7 108 mhz 108 mhz 100 mhz [4] 8C15 108 mhz 108 mhz 108 mhz note 4. this parameter is guaranteed by characterization; not tested in production.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 16 of 90 quad data width (quad) cr1 [1] when set to 1, this bit switches the data width of the device to 4 i/os C quad mode, that is wp becomes i/o2 and reset / (i/o3) becomes i/o3. i f the alternate function is enabled on i/ o3 by setting io3r bit i n configuration register 2 (cr2[5]), reset / (i/o3) works as i/o3 when cs is low and reset input when cs is high. the wp input is disabled and is internally set to 1. the quad bit must be set to 1 when executing the extended spi read commands: quad output read, and quad i/o read. the impact of quad bit setting on various spi interfaces are shown in table 16 on page 17 . configuration register 2 (cr2) configuration register 2 as shown in ta b l e 1 4 controls the interface functions. the cr2 is a nonvolatile register and is accessible by the wrar command for write and the rdcr2 or the rdar command for read operations. the cr2 access details are provided in register access commands on page 24 . the default state shown after each bit in ta b l e 1 4 is the factory set value. quad spi (qpi) cr2 [6] this bit controls the instruct ion and data widths in quad spi m ode. in this mode, all transfers between the h ost system and me mory are 4 bits wide on i/o0 to i/o3, including all instructions. th e quad bit set 1 in cr1 [1] i s not necessary for the qpi mode . refer to table 17 on page 17 for details. table 14. configuration register 2 (cr2) cr2[7] cr2[6] cr2[5] cr2[4] cr2[3] cr2[2] cr2[1] cr2[0] rfu (0) qpi (0) io3r (0) dpi (0) r fu (0) rfu (0) rfu (0) rfu (0) table 15. configuration register 2 (cr2) details bit bit name bit function type read/write description cr2[7] rfu reserved (0) reserved for future use cr2[6] qpi quad spi enable nv r/w 1 = enable qpi protocol 0 = enable spi protocol, if dpi bit is set to 0 cr2[5] io3r io3 reset nv r/ w 1 = i/o3 is used as reset input when cs is high 0 = i/o3 has no alternate function cr2[4] dpi dual spi enable nv r/w 1 = enable dpi protocol 0 = enable spi protocol, if qpi bit is set to 0 cr2[3] rfu reserved (0) reserved for future use cr2[2] rfu reserved (0) reserved for future use cr2[1] rfu reserved (0) reserved for future use cr2[0] rfu reserved (0) reserved for future use nv - nonvolatile
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 17 of 90 io3 reset (io3r) cr2 [5] this bit controls the reset / (i/o3) pin behavior. when this bit is set 1, enables the reset input during normal operation. ta b l e 1 6 shows the reset / (i/o3) functionality based on the interface mode. dual (dpi) cr2 [4] this bit controls the instruction and data widths in dual spi mode. in this mode, all transfe rs between the host system and memory are 2 bits wide on i/o0 to i/o1, including all instructi ons. refer to table 17 for details. table 16. reset / (i/o3) pin function interface mode quad bit (cr1 [5] ) reset / (i/o3) pin function io3r (cr2[5]) = 0 (io3 reset disable) io3r (cr2[5]) = 1 (io3 reset enable) cs = 0 cs = 1 cs = 0 cs = 1 spi quad = 0 no func tion no function reset reset spi quad = 1 i/o3 [6] no function i/o3 [6] reset dpi quad = 0 no func tion no function reset reset dpi quad = 1 no function no function no function reset qpi quad = x (dont care) i/o3 no function i/o3 reset table 17. spi operation modes setting quad [7] cr1 [5] dpi cr2 [4] qpi cr2 [6] operational mode 0 0 0 spi, extended spi (dual) 1 0 0 spi, extended spi (dual/quad) x1 0dpi x0 1qpi 0 1 1 spi [8] , extended spi (dual) C not a recommended configuration 1 1 1 spi [8] , extended spi (dual/q uad) - not a recommended configuration notes 5. all extended spis start in the spi mode. 6. no function in spi and dpi modes. i/o3 in quad data or quad i /o mode. 7. quad = 1 reconfigures i/o to quad mode and affects wp and reset operations, refer to table 16 for details. 8. register reads will always re turn what is written to them, ev en though not a recommended configuration.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 18 of 90 configuration register 4 (cr4) the configuration register 4 (cr4) as shown in table 18 controls the output drive impedance and the deep-power-down (d pd) mode setting. the cr4 is a nonvolatile register and is accessib le by the wrar command for write and the rdcr4 or the rdar command for read operations. the cr4 access details are provide d in register access commands on page 24 . the default state shown after each bit in ta b l e 1 8 is the factory set value. output impedance (oi) cr4 [7:5] these three bits control the output impedance (drive strength) of the i/o pins. the output impeda nce configuration bits enable the user to adjust the dr ive strength for a better signal integrity on the printed circuit board. deep-power-down mode o n por (dpdpor) cr4 [2] this bit controls whether the device will enter the deep-power- down (dpd) or the standby mode after the completion of power-on-reset (por), hardware reset (reset pin or jedec reset), or exit t he hibernate mode. the dpdpor co nfiguration bit enables the device to start in dpd mode, instead of standby mod e when cs is high. a cs pulse-width of t csdpd , or hardware reset will exit the dpd mode after t extdpd time. the cs pulse-width can be generated by a dummy command cycle or toggl ing cs alone while sck and i/os are dont care. the dpdpor bit status is ign ored during the software reset and the device always enters sta ndby after the software reset. table 18. configuration register 4 (cr4) cr4[7] cr4[6] cr4[5] cr4[4] cr4[3] cr4[2] cr4[1] cr4[0] oi (0) oi (0) oi (0) rfu (0) rfu (1) dpdpor (0) rfu (0) rfu (0) table 19. configuration register 4 (cr4) details bit bit name bit function type read/write description cr4[7] oi output impedance nv r/w output impedance selection cr4[6] nv r/w cr4[5] nv r/w cr4[4] rfu reserved (0) reserved for future use cr4[3] rfu reserved (1) reserved for future use [9] cr4[2] dpdpor deep power-down mode on por nv r/w 1 = deep power-down is entered upon completion of por o r hardware reset (including jedec reset) when cs is high 0 = standby mode is entered upon completion of power-up or por o r hardware reset (including jedec reset) when cs is high cr4[1] rfu reserved (0) reserved for future use cr4[0] rfu reserved (0) reserved for future use table 20. impedance selection impedance selection typical impedance (?) [10] comments 000 45 30 ? is the factory default configuration. other drive strength can be programmed by writing into impedence selection bits in cr4[7:5]. 001 120 010 90 011 6 0 100 45 101 3 0 110 20 111 notes 9. the spi bus master must make su re bit cr4 [3] remains 1 whe n writing to this configuration register. writing a 0 to this bit may impact device functionality. 10. typical impedance measured at v dd /2.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 19 of 90 configuration register 5 (cr5) configuration register 5 as shown in table 21 controls the register read latency (dummy cycles) configuratio n. the cr5 is a nonvolatile register and is acce ssible by the wrar command for write and the rdcr5 or the rdar command for read operations. the cr5 access details are provided in register access commands on page 24 . the default state shown after each bit in ta b l e 2 1 is the factory set value. register latency code (rlc [1:0]) cr5 [7:6] these two bits control the read latency (dummy cycle) delay in all variable latency register read instructions. it enables the user to adjust the read latency during normal operation to optimize the latency for different register read instructions at different operating frequencies. table 23 shows latency cycles for register read command. table 21. configuration register 5 (cr5) cr5[7] cr5[6] cr5[5] cr5[4] cr5[3] cr5[2] cr5[1] cr5[0] rlc1 (0) rlc0 (0) rfu (0) rfu (0) rfu (0) rfu (0) rfu (0) rfu (0) table 22. configuration register 5 (cr5) details bit bit name bit function type read/write description cr5[7] rlc1 register latency code nv r/w selects number of register read latency cycles between 0 to 3 clock cycles for register accesses cr5[6] rlc0 r/w cr5[5] rfu reserved (0) reserved for future use cr5[4] rfu reserved (0) reserved for future use cr5[3] rfu reserved (0) reserved for future use cr5[2] rfu reserved (0) reserved for future use cr5[1] rfu reserved (0) reserved for future use cr5[0] rfu reserved (0) reserved for future use table 23. dummy cycles for register read commands latency (dummy cycles) spi (sdr) dpi (sdr) qpi (sdr) rdsr1, rdsr2, rdcr1, rdcr2, rdcr4, rdcr5, rdar, ruid, rdid2, rd sn 050 mhz [11] 50 mhz [11] 50 mhz [11] 1C3 108 mhz 108 mhz 108 mhz note 11. this parameter is guaranteed by characterization; not tested in production.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 20 of 90 functional description the cy15x104qsn has an 8-bit inst ruction register. all instruc- tions and their opcodes are listed in the following. all instru ctions, addresses, and data are transferred with a high to low cs transition. furthermore, the wp and reset pins provide additional hardware controlled functions. command structure the cy15x104qsn command cycle consists of up to five different command phases - opcode, address, mode, dummy (latency), and data. the number of command phases per command cycle varies from one t o five depending on the opcode sent in the opcode phase. the opcode, address, mode, and data phases are configurable in terms of number of lines 1, 2, or 4 needed to transmit them in spi, dpi, or qpi interface, respec - tively. table 24 shows the command p hases for each command cycle in differen t spi interfaces. there are 44 commands, called opcodes that can be issued by the bus master to the cy15x104qsn as shown in ta b l e 2 5 . these opcodes control the function s performed by the memory. table 24. command transmission over i/os in different spi mode s command phases command transmission on i/os single channel spi extended spi multi-channel spi dual data quad data dual i/o quad i/o dpi qpi opcode si i/o0 i/o0 i/o0 i/o0 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 address si i/o0 i/o0 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 mode si i/o0 i/o0 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 dummy (latency) fixed number of dummy spi clocks, independent of spi interface. 0 to 15 clocks for me mory access (configur able via cr1[7:4]) 0 to 3 clocks for register acce ss (configurable via cr5[7:6]) data si/so i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 i/o0, i/o1 i/o0, i/o1, i/o2, i/o3 table 25. opcode commands command spi bus interface data transfer latency xip command opcode (hex) spi dual data quad data dual i/o quad i/o dpi qpi sdr register latency memory latency execute -in-place write enable control wren 06 yes na yes yes yes na na na wrdi 04 yes na yes yes yes na na na register access rdsr1 05 yes na yes yes yes yes na na rdsr2 07 yes na yes yes yes yes na na rdcr1 35 yes na yes yes yes yes na na rdcr2 3f yes na yes yes yes yes na na rdcr4 45 yes na yes yes yes yes na na rdcr5 5e yes na yes yes yes yes na na wrar 71 yes na yes yes yes na na na rdar 65 yes na yes yes yes yes na na memory read read 03 yes na yes yes yes na na na fast_read 0b yes na yes yes yes na yes yes dor 3b na yes na yes na yes yes
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 21 of 90 dior bb na yes na yes na yes yes qor 6b na yes na yes na yes yes qior eb na yes na yes yes na yes yes memory write write 02 yes na yes yes yes na na na fast_write da yes na yes yes yes na na yes diw a2 na yes na yes na na yes diow a1 na yes na yes na na yes qiw 32 na yes na yes na na yes qiow d2 na yes na yes na na yes special sector memory access sswr 42 yes na yes yes yes na na na ssrd 4b yes na yes yes yes na yes na ecc and crc clecc 1b yes na yes yes yes na na na eccrd 19 yes na yes yes yes na yes na crcc 5b yes na yes yes yes na na na epcs 75 yes na yes yes yes na na na epcr 7a yes na yes yes yes na na na identification & serial number ruid 4c yes na yes yes yes yes na na rdid 9f yes na yes yes yes yes na na wrsn c2 yes na yes yes yes yes na na rdsn c3 yes na yes yes yes yes na na power modes and reset dpd b9 yes na yes yes yes na na na hbn ba yes na yes yes yes na na na rsten 66 yes na yes yes yes na na na rst 99 yes na yes yes yes na na na table 25. opcode commands (continued) command spi bus interface data transfer latency xip command opcode (hex) spi dual data quad data dual i/o quad i/o dpi qpi sdr register latency memory latency execute -in-place
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 22 of 90 write enable control commands these commands set or clear the write enable latch bit in the s tatus register 1 (sr1[1]). set write enable latch (wren, 06h) the wren command sets the wel bit of status register 1 (sr1[1]) to a 1. cy15x104qsn requires wel bit set to a 1 prior to issuing any write command. the cy15x104qsn commands requiring wel set to 1 prior to their execution are wrar, write, fast_write, diw, diow, qiw, qiow, sswr, and wrsn. cs must be driven to the logic high state after the eighth bit of the instruction byte has been latched in on si. cy15x104qsn executes the wren command and sets the wel bit (sr1[1]) to 1 after cs is driven high after 8-bit wren opcode is successfully latched in. figure 7. wren bus configuration in spi mode figure 8. wren bus configuration in dpi mode table 26. write enable control commands command opcode (hex) command description wren 06 write enable C sets the wel bit of status register 1 to 1 wrdi 04 write disable C clears the wel bit of status register 1 t o 0 table 27. write enable control command details opcode (hex) address length spi bus interface data transfer xip latency max clock frequency spi dual data quad data dual i/o quad io dpi qpi sdr execute -in-place dummy cycles 06 0 yes na yes yes yes na na 108 mhz 04 0 yes na yes yes yes na na 108 mhz opcode (06h) hi -z hi-z x cs sck si (io0) so (io1) x 0 0 0 0 0 1 1 0 opcode (06h) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 0 0 0 0 0 1 1 0
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 23 of 90 figure 9. wren bus configuration in qpi mode reset write enable latch (wrdi, 04h) the wrdi instruction clears the write enable latch (wel) bit of the status register 1 (sr1[1]) to a 0. this disables write an y register (wrar), special sector write, and other instructions that require wel to be set to 1 prior to the execution. the w rdi instruction can be used to protect the memory and the spi registers against inadvertent writes. the wrdi command is ignored during an embedded operation while wip bit = 1. cs must be driven to the logic high state after the eighth bit of the instruction byte has been latched in on si. cy15x104qsn executes the wrdi command and clears the wel bit (sr1[1]) to 0 after cs is driven high after 8-bit wrdi opcode is successfully latched in. figure 10. wrdi bus configuration in spi mode figure 11. wrdi bus con figuration in dpi mode figure 12. wrdi bus configuration in qpi mode opc. (06h) hi-z hi-z hi-z hi-z hi -z hi -z hi -z hi -z cs sck si (io0) so (io1) wp (io2) reset (io3) 0 0 0 0 0 1 1 0 opcode (04h) hi -z hi-z x cs sck si (io0) so (io1) x 0 0 0 0 0 1 0 0 opcode (04h) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 0 0 0 0 0 1 0 0 opc. (04h) hi-z hi-z hi-z hi-z hi -z hi -z hi -z hi -z cs sck si (io0) so (io1) wp (io2) reset (io3) 0 0 0 0 0 1 0 0
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 24 of 90 register access commands cy15x104qsn provides various configuration and status registers. these registers are user-writable, which can be programmed to enable or disable certain configurations/features in the part as well as can be polled to know the device status. these registers are accessed by specific commands, called opcodes. the individual register bits can be one of multiple types: write/read, read only, or reserved for future use (rfu). the specific type of each bit is specified in their respective regi ster section. register bits can be either volatile or nonvolatile in nature. all volatile (v) bits are set to their default values a fter power-on reset (por), or any reset event (via hardware or software resets); while all nonvolatile (nv) bits resume to use r configured values after power-on reset (por), or any reset even t (via hardware or software resets). table 28. register access commands command opcode (hex) command description rdsr1 05 read status register 1 rdsr2 07 read status register 2 rdcr1 35 read configuration register 1 rdcr2 3f read configuration register 2 rdcr4 45 read configuration register 4 rdcr5 5e read configuration register 5 wrar 71 write any register - inclu ding status registers, configur ations registers, serial number registers rdar 65 read any register - including status registers, configura tions registers, crc reg isters, ecc registers, serial number registers, and id registers table 29. register access command details opcode (hex) address length spi bus interface data transfer register latency max clock frequency register latency spi dual data quad data dual i/o quad i/o dpi qpi sdr dummy cycle 01 0 yes na yes yes yes na 108 mhz na 05 0 yes na yes yes yes yes 108 mhz yes 07 0 yes na yes yes yes yes 108 mhz yes 35 0 yes na yes yes yes yes 108 mhz yes 3f 0 yes na yes yes yes yes 108 mhz yes 45 0 yes na yes yes yes yes 108 mhz yes 5e 0 yes na yes yes yes yes 108 mhz yes 71 3 bytes yes na yes yes yes na 108 mhz na 65 3 bytes yes na yes yes yes yes 108 mhz yes
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 25 of 90 read status regist er 1 (rdsr1, 05h) the rdsr1 command allows the bus master to verify the contents of the status register 1 (sr1). r eading sr1 provides informatio n about the current state of the wr ite-protection features, wel, and wip status. following the rdsr1 opcode, the cy15x104q will return one byte sr1 content. note: the dummy cycles shown are a conf iguration option through regis ter latency code bits (rlc0, rlc1) in cr5. figure 13. read sr1 (rdsr1) in spi mode figure 14. read sr1 (rdsr1) in dpi mode figure 15. read sr1 (rdsr1) in qpi mode read status regist er 2 (rdsr2, 07h) 0 0 0 0 0 1 0 1 opcode (05h) status register 1 hi -z x dummy cycles cs sck si (io0) so (io1) dm 1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 0 0 0 0 1 0 1 opcode (05h) status register 1 hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 hi-z hi-z d3 d2 d1 d0 d u m m y c y c l e s dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 0 0 0 0 0 1 0 1 opc. (05h) status reg. 1 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm 0 dm1 dm0 dm1 dm 0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 26 of 90 the rdsr2 command allows the bus master to verify the contents of the status register 2 (sr2). this is a read only register an d provides information about the crc suspend and crc abort status . the sr2 bits indicate the correct status (crcs and crca) only when the wip bit of sr1 is 0 . reading sr2 while wip is 1 wi ll return an undetermined status. note: the dummy cycles shown are a co nfiguration optio n through regi ster latency code bits (rlc0, rlc1) in cr5. figure 16. read sr2 (rdsr2) in spi mode figure 17. read sr2 (rdsr2) in dpi mode 0 0 0 0 0 1 1 1 opcode (07h) status register 2 hi-z x dummy cycles cs sck si (io0) so (io1) dm1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 0 0 0 0 1 1 1 opc. (07h) status reg. 2 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 27 of 90 figure 18. read sr2 (rdsr2) in qpi mode read configuration r egister 1 (rdcr1, 35h) the rdcr1 command allows the bus master to verify the contents of the configuration register 1 (cr1). reading cr1 provides information about the current sta te of the memory latency code, lock status of block protects bits and quad bit status. follow ing the rdcr1 opcode, cy15x104qsn will return one byte c ontent of cr1. note: the dummy cycles shown are a co nfiguration optio n through regi ster latency code bits (rlc0, rlc1) in cr5. figure 19. read cr1 (rdcr1) in spi mode figure 20. read cr1 (rdcr1) in dpi mode 0 0 0 0 0 1 1 1 opc. (07h) status reg. 2 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 0 0 1 1 0 1 0 1 opcode (35h) config register 1 hi-z x dummy cycles cs sck si (io0) so (io1) dm1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 0 1 1 0 1 0 1 opcode (35h) config register 1 hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 hi-z hi-z d3 d2 d1 d0 d u m m y c y c l e s dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 28 of 90 figure 21. read cr1 (rdcr1) in qpi mode read configuration r egister 2 (rdcr2, 3fh) the rdcr2 command allows the bus master to verify the contents of the configuration register 2 (cr2). reading cr2 provides information about the current spi interface option (spi vs dpi vs qpi) and reset / (i/o3) status. following the rdcr2 opcode, the cy15x104qsn will return one byte content of cr2. note: the dummy cycles shown are a conf iguration option through regis ter latency code bits (rlc0, rlc1) in cr5. figure 22. read cr2 (rdcr2) in spi mode figure 23. read cr2 (rdcr2) in dpi mode 0 0 1 1 0 1 0 1 opc. (35h) config reg. 1 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 0 0 1 1 1 1 1 1 opcode (3fh) config register 2 hi-z x dummy cycles cs sck si (io0) so (io1) dm1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 0 1 1 1 1 1 1 opcode (3fh) config register 2 hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 hi-z hi-z d3 d2 d1 d0 d u m m y c y c l e s dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 29 of 90 figure 24. read cr2 (rdcr2) in qpi mode read configuration r egister 4 (rdcr4, 45h) the rdcr4 command allows the bus master to verify the contents of the configuration register 4 (cr4). reading cr4 provides information about the output im pedance setting and device power mode status after por (deep-power-down vs standby). following the rdcr4 opcode, the cy15x104qsn will retur n one byte content of cr4. note: the dummy cycles shown are a co nfiguration optio n through regi ster latency code bits (rlc0, rlc1) in cr5. figure 25. read cr4 (rdcr4) in spi mode figure 26. read cr4 (rdcr4) in dpi mode 0 0 1 1 1 1 1 1 opc. (3fh) config reg. 2 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 0 1 0 0 0 1 0 1 opcode (45h) config register 4 hi-z x dummy cycles cs sck si (io0) so (io1) dm1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 1 0 0 0 1 0 1 opcode (45h) config register 4 hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 hi-z hi-z d3 d2 d1 d0 d u m m y c y c l e s dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 30 of 90 figure 27. read cr4 (rdcr4) in qpi mode read configuration r egister 5 (rdcr5, 5eh) the rdcr5 command allows the bus master to verify the contents of the configuration register 5 (cr5). reading cr5 provides information about the register r ead latency cycles (rlc0, rlc1) setting. following the rdcr5 opc ode, the cy15x104qsn will retu rn one byte content of cr5. note: the dummy cycles shown are a co nfiguration optio n through regi ster latency code bits (rlc0, rlc1) in cr5. figure 28. read cr5 (rdcr5) in spi mode figure 29. read cr5 (rdcr5) in dpi mode 0 1 0 0 0 1 0 1 opc. (45h) config reg. 4 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 0 1 0 1 1 1 1 0 opcode (5eh) config register 5 hi-z x dummy cycles cs sck si (io0) so (io1) dm1 dm6 dm0 dm7 d7 d6 d5 d4 hi-z x d3 d2 d1 d0 dm5 dm3 dm4 dm2 hi-z 0 1 0 1 1 1 1 0 opcode (5eh) config register 5 hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 hi-z hi-z d3 d2 d1 d0 d u m m y c y c l e s dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 31 of 90 figure 30. read cr5 (rdcr5) in qpi mode write any regist er (wrar, 71h) the wrar instruction allows writing into cy15x104qsn registers, one register at a time, addressable by their 3-byte addressing (with upper two most significant address bytes set t o 0). the wrar opcode is followed by the three-byte address of the register, as shown in table 31 on page 32 , followed by one byte register data to be written. the wren command precedes the wrar command to set the wel bit 1 prior to wrar. the wel bit is automatically cleared to 1 after wrar command is terminated (at the rising edge of cs ). the wrar command is ignored when the srwd bit in sr1 (sr1[7]) is set to 1 and the wp pin is driven low. note: the wrar command supports only one byte write per wrar command at the given register address. the wrar command format is shown in ta b l e 3 0 . figure 31. write any regi ster (wrar) in spi mode 0 1 0 1 1 1 1 0 opc. (5eh) config reg. 5 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 table 30. registers with generic write instructions instruction name instruction description opcode address bytes data bytes wrar write any register 71h 3 1 op 7 op 6 op 1 op 0 a23 a22 a1 a0 opcode (71h) address (3 bytes) data (1 byte) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z x cs sck si (io0) so (io1) x
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 32 of 90 figure 32. write any re gister (wrar) in dpi mode figure 33. write any register (wrar) in qpi mode a23 a22 a21 a20 a3 a2 a1 a0 opcode (71h) address (3 bytes) data (1 byte ) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 a23 a22 a21 a20 a3 a2 a1 a0 opc. (71h) address (3 bytes) data (1 byte) d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 table 31. register address for generic register access function register type wrar & rdar command register address [12] volatile (v)/ nonvolatile (nv) [12] device status status register 1 wrar & rdar 0x000000 nv status register 2 rdar 0x000001 v device configuration configuratio n register 1 wrar & rdar 0x000002 nv configuration register 2 wrar & rdar 0 x000003 nv configuration register 4 wrar & rdar 0x000005 nv configuration register 5 wrar & rdar 0x000006 nv note 12. the volatile (v) registers return to their default state aft er por or any reset (hardware and software) event. refer to table 53 on page 72 for the volatile register status after any por or reset event.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 33 of 90 note: these registers do not share the main memory address space of cy15x104qsn. the third most s ignificant (ms) byte xx is a dont care byte in three bytes register address. the nonvolat ile (nv) registers survive the power cycles and can be changed only by overwriting with a new val ue by using wrar command. read any register (rdar, 65h) the rdar instruction allows read ing cy15x104qsn registers, one register at a time, addressable by their 3-byte addressing (wit h upper two most significant address bytes set to 0). the rdar op code is followed by the three-byte address of the register and dummy cycle (per register latency set in cr5), after which cy15x104qs n returns one byte register content on its output bus. the host should terminate the rdar command by pulling cs high after one register byte is received. keeping cs low after the first data byte received will return undefined data byte(s). the rdar instructi on timing diagram s are shown in figure 34 to figure 36 on page 34 . note: the dummy cycles shown are a co nfiguration optio n through regi ster latency code bits (rlc0, rlc1) in cr5. figure 34. read any regis ter (rdar) in spi mode error correction ecc stat us register rdar 0x000089 v ecc count register [7:0] rdar 0x00008a v ecc count register [15:8] rdar 0x00008b v ecc address trap regist er [7:0] rdar 0x00008e v ecc address trap regist er [15:8] rdar 0x00008f v ecc address trap regist er [23:16] rdar 0x000040 v ecc address trap regist er [31:24] rdar 0x000041 v cyclic redundancy check crc register [7: 0] rdar 0x000095 v crc register [15:8] rdar 0x000096 v crc register [23:16] rdar 0x000097 v crc register [31:24] rdar 0x000098 v table 31. register address for generic register access (continued) function register type wrar & rdar command register address [12] volatile (v)/ nonvolatile (nv) [12] op 7 op 6 op 1 op 0 a23 a22 a1 a0 opcode address (3 bytes) read data dummy cycles d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z dm1 dm6 dm0 dm7 x x cs sck si (io0) so (io1)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 34 of 90 figure 35. read any regis ter (rdar) in dpi mode figure 36. read any reg ister (rdar) in qpi mode a23 a22 a21 a20 a3 a2 a1 a0 opcode address (3 bytes) read data d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 a23 a22 a21 a20 a3 a2 a1 a0 opc. address (3 bytes) read data d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 35 of 90 memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash, the cy15x104qsn can perform sequential writes at bus speed. no page register is needed and any number of sequential writes can be performed. memory write operation the memory write instruction is sent after the cs pin is pulled low. the write opcode is followed by a three-byte address and mode byte for xip (as applicable). the cy15x104qsn has a 19-bit address space for 4-mbit (512k 8) density. the most significant address byte contains a16, a17, and a18 active bits while the remaining a[23:19] bits are considered dont care. address bits a18 to a0 are transmitted in three bytes over the spi bus, following the (xip) mode byte, if supported. immedi- ately after the last address bit or the last mode bit (if xip i s supported) is transmitted, the data byte(s) ([d7:0]) is (are) t rans- mitted through the input line (s). the memory write operations are allowed in spi, extended spi, dpi or qpi modes in sdr bus interface and some of them support execute-in-place (xip). ta b l e 3 2 shows the list of memory write commands supported in cy15x104qsn in various spi bus interface and data transfer modes. notes: when a burst write reaches a protected block address, it continues incrementing the address into the protected space but does not write any data to the protected memory. if the address rolls over and takes the burst write to unprotected space, it resumes writes. the same operation is true if a burst write is initiated within a write-protec ted block. if the power is lost in the middl e of the byte transfer during the write operation, only the last completed by te will be written. table 32. memory write commands command opcode (hex) command description write 02 memory write - write to f-ram array fast_write da memory fast write - m emory write with execute-in-pl ace diw a2 dual input write - command, address and mode byte are sent on s ingle si line, data bytes are sent on dual input lines i/o1 (so), i/o0 (si) qiw 32 quad input write - command, addre ss and mode byte s are sent on single si line, data bytes are sent on quad input lines i/o3 (reset ), i/o2 (wp ), i/o1 (so), i/o0 (si) qiow d2 quad i/o write - command is sent on single si line, address and mode byte and data bytes are sent on quad input lines i/o3 (reset ), i/o2 (wp ), i/o1 (so), i/o0 (si) table 33. memory write command details command spi bus interface data transfer xip max clock frequency command opcode (hex) ad- dress length spi dual data quad data dual i/o quad io dpi qpi sdr execute- in-place (mode byte) write 02 3 bytes yes na yes yes yes na 108 mhz fast_write da 3 bytes yes na yes yes yes yes 108 mhz diw a2 3 bytes na yes na yes yes 108 mhz diow a1 3 bytes na yes na yes yes 108 mhz qiw 32 3 bytes na yes na yes yes 108 mhz qiow d2 3 bytes na yes na yes yes 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 36 of 90 write (write, 02h) write operations are preformed when the write opcode, along with write data, are transmitted on the si pin for spi mode, or i/o1 and i/o0 pins for dpi mode, or i/o3, i/o2, i/o1, and i/o0 pins for qpi mode. the burst writ es can be used to write consec - utive addresses without issuing a new write instruction. if onl y one byte is to be written, the cs pin must be driven high after the d0 (lsb of data) is transmit ted. however, if more bytes are to be written, cs pin must be held low and the address is incre- mented automatically. the data bytes on the input pin(s) are written in successive addresses. when the internal address counter reaches to 0x7ffff, th e address rolls over to 0x00000 and the device continues to write. notes: the write instruction will only execute if the wel bit (sr1[1]) is set to 1. the wel bit (sr1[1]) does not clear to 0 on completion of the write operation. therefore, any write command following the write operation doesnt require preceding wren command to set the wel bit to 1. figure 37. memory write (write) in spi mode figure 38. memory write (write) in dpi mode opcode (02h) address (3 bytes) write data 0 0 0 0 0 0 1 0 a23 a22 a21 am-3 a3 a2 a1 a0 x cs sck si (io0) so (io1) hi-z hi-z write data x hi-z hi-z data byte 1 data byte 2 data byte n cs sck si (io0) so (io1) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 a23 a22 a21 a20 a3 a2 a1 a0 opcode (02h) address (3 bytes) write data d7 d6 d5 d4 d0 d1 d2 d3 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 d0 d1 d2 d3 data byte 1 data byte 2 data byte n d7 d6 d5 d4 d0 d1 d2 d3
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 37 of 90 figure 39. memory write (write) in qpi mode 0 0 0 0 0 0 1 0 a23 a22 a21 a20 a3 a2 a1 a0 opc. (02h) address (3 bytes) write data d7 d6 d5 d2 d3 d1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d2 d3 d1 data byte 1 data byte 2 data byte n d4 d0 d4 d0 d7 d3 d6 d2 d5 d1 d4 d0
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 38 of 90 fast write (fast_write, dah) the fast_write instruction is similar to write instruction except for it allows for xip operation set through mode byte. mode bits allow a series of fast write instructions to eliminat e the 8-bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), reduces initial access time s (improves performance). the mode bits control the length of the next fast write operation through the inclusion or exclusion of the first byte instructio n opcode. if the mode bits are axh the device transitions to continuous fast write mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the dah opcode thus eliminating 8-cycles from the instruction sequence. oth erwise, opcode is required once cs transitions from high to low. notes: mode bits with !axh ( logical not of axh b yte) will exit the fast_write xip mode. fast_write instruction can only be executed by the device if the write enable latch (wel) in the status register is set t o 1 to enable write operations. the wel bit does not reset t o 0 on completion of the fast_write operation. figure 40. fast write (fast_write) in spi mode figure 41. fast write (fast_write) in dpi mode figure 42. fast write (fast_write) in qpi mode 1 1 1 0 a23 a22 a1 a0 opcode (dah) address (3 bytes) write data (n bytes) mode byte d7 d6 d5 d0 d7 d0 hi-z x m1 m6 m0 m7 cs sck si (io0) so (io1) hi-z hi-z 1 1 0 1 1 0 1 0 a23 a22 a21 a20 a3 a2 a1 a0 opcode (dah) address (3 bytes) write data (n bytes) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) mode byte m2 m4 m0 m6 m3 m5 m1 m7 1 1 0 1 1 0 1 0 a23 a22 a21 a20 a3 a2 a1 a0 opc. (dah) address (3 bytes) write data (n bytes ) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) mode byte m2 m4 m0 m6 m3 m5 m1 m7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 39 of 90 dual input write (diw, a2h) the diw instruction can be used in dual data mode which is part of the extended spi write instructions. in dual data mode, opcode, address and mode bytes are transmitted through si pin, one bit per clock cycle. immedia tely after the last address bit is transmitted, the pins are reconfigured as so becoming i/o1, and si becoming i/o0, and the data (d[7:0]) is transmitted into the i/o1, and i/o0 pins, 2 bits per clock cycle, starting with d7 o n i/o1 and d6 on i/o0. mode bits allow a series of diw instructions to eliminate the 8 -bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), and reduces initial access times (improves performance). the mode bits control the lengt h of the next diw operation through the inclusion or exclusion of the first byte instructio n opcode. if the mode bits are axh the device transitions to continuous diw mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the a2h op code thus eliminating 8 cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: mode bits with !axh (logical no t of axh byte) will exit the diw xip mode. diw instruction can only be executed by the device when the wel bit is set to 1 to enable write operations. the wel bit does not reset to 0 on completion of the diw operation. figure 43. dual input write (diw) 1 0 1 0 a23 a22 a1 a0 opcode (a2h) address (3 bytes) write data (n bytes) mode byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z m1 m6 m0 m7 cs sck si (io0) so (io1)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 40 of 90 dual i/o write (diow, a1h) the diow instruction can be used in dual addr/data mode, which is part of extended spi w rite instructions. in dual addr/data mode, the opcode is t ransmitted through the si pin, one bit per clock cycle. immediat ely after the last opcode bit is transmitted, the pins are reconfigured as so becoming i/o1, and si becoming i/o0, and the address along with the mode byte are transmitted into the part through i/o1 and i/o0 pins, 2 bits pe r clock cycle, starting with address a23 on i/o1, a22 on i/o0, un til the three-byte address is input. after the last address bits ar e transmitted, the data (d[7:0]) is transmitted into the part thr ough i/o1 and i/o0 two bits per clock cycle starting with d7 on i/o1 and d6 on i/o0. mode bits allow a series of diow instructions to eliminate the 8-bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), significantly reduces initial access times (improves per for- mance). the mode bits control the length of the next diow operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous diow mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the a1h op code thus eliminating 8 cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: mode bits with !axh (logical not of axh byte) will exit the dio w xip mode. the diow instruction can only be executed by the device when the wel bit set to 1 to enable write operations. the wel bit does not reset to 0 on completion of the diow operation. figure 44. dual i/o write (diow) 1 0 0 1 opcode (a1h) write data (n bytes) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 mode byte a23 a22 a21 a20 a3 a2 a1 a0 address (3 bytes) hi-z hi-z hi-z hi-z m2 m4 m0 m6 m3 m5 m1 m7 cs sck si (io0) so (io1)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 41 of 90 quad input write (qiw, 32h) the qiw instruction is used in quad data mode which is part of extended spi write instructions. in quad data mode, opcode, address, and mode bytes are transmitted through the si pin, one bit per clock cycle. immediately after the last address bit is transmitted, the pins are reconfigured as reset becoming i/o3, wp becoming i/o2, so becoming i/o1, and si becoming i/o0, and the data (d7-d0) is transm itted into the i/o3 i/o2, i/o1, a nd i/o0 pins, 4 bits per clock cycle, starting with d 7 on i/o3 and d6 on i/o2, d5 on i/o1, and d4 on i/o0. mode bits allow a series of qiw instructions to eliminate the 8 -bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), significantly reduces initial access times (improves per for- mance). the mode bits control the length of the next qiw operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous qiw mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the 32h opcode thus eliminating 8 cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: mode bits with !axh (logical no t of axh byte) will exit the qiw xip mode. the qiw instruction can only be executed by the device if the write enable latch (wel) in the status register is set to 1 t o enable write operations. the wel bit does not reset to 0 on completion of the qiw operation. figure 45. quad input write (qiw) 0 0 1 0 a23 a22 a1 a0 opcode (32h) address (3 bytes) write data (n bytes) mode byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x hi-z hi-z hi-z hi-z hi-z hi-z hi-z m1 m6 m0 m7 cs sck si (io0) so (io1) wp (io2) reset (io3)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 42 of 90 quad i/o write (qiow, d2h) the qiow instruction can be used in quad addr/data mode which is part of extended spi write instructions. in quad addr/data mode, opcode is transmitted through si pin, one bit per clock cycle. immediately af ter the last o pcode bit is transmitted, the pins are reconfigured as reset becoming i/o3, wp becoming i/o2, so becoming i/o1, and si becoming i/o0, and the address is transmitted into the part through i/o3, i/o2 , i/o1 and i/o0 pins, 4 bits per clock cycle, starting with addre ss a23 on i/o3, a22 in i/o2, a21 on i/o1 and a20 on i/o0, until th e three-byte address is input. after the last address bits are transmitted, the data (d7-d0) is transmitted into the part thro ugh i/o3, i/o2, i/o1, and i/o0 four bits per clock cycle starting w ith d7 on i/o3, d6 on i/o2, d5 on i/o1 and d4 on i/o0. mode bits allow a series of qiow instructions to eliminate the 8-bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), significantly reduces initial access times (improves per for- mance). the mode bits control the length of the next qiow operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous diow mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the d2h opc ode thus eliminati ng 8 cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: mode bits with !axh (logical not of axh byte) will exit the qio w xip mode. the qiow instruction can only be executed by the device if the write enable latch (wel) in the status register is set to 1 t o enable write operations. the wel bit does not reset to 0 on completion of the qiow operation. figure 46. quad i/o write (qiow) 1 1 1 0 opcode (d2h) write data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a23 a22 a21 a20 a3 a2 a1 a0 address (3 bytes) mode byte hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z m2 m4 m0 m6 m3 m5 m1 m7 cs sck si (io0) so (io1) wp (io2) reset (io3)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 43 of 90 memory read operation the memory read instruction is sent after the cs pin is pulled low to select a device. the read opcode is followed by a three-byte address and mode byte for xip (as applicable). the cy15x104qsn has a 19-bit address space for 4-mbit (512k 8) density. the most significant a ddress byte contains a16, a17, and a18 active bits while the remaining bits are considered 'do n't care'. address bits a18 to a0 are transmitted as three bytes ov er the spi bus followed by the mode byte and dummy cycles as applicable. the memory read supports spi, extended spi, dpi, or qpi modes in sdr bus interface and includes execute-in-place (xip) support. ta b l e 3 4 shows the list of memory read commands supported in cy15x104qsn in various spi bus interface and data transfer modes. table 34. memory read commands command opcode (hex) command description read 03 memory read - reads up to 50 mhz without memory latency cycle i n spi sdr mode and up to 108 mhz with memory latency cycles in spi, dpi, qpi sdr modes fast_read 0b memory fast read - read s up to 108 mhz with memory l atency cycles in spi, dpi, qpi sdr modes dor 3b dual output read - command and address bytes are sent on single si line and data on dual output lines i/o1 (so), i/o0 (si) dior bb dual i/o read - command sent on single si line, address input a nd data output on dual output lines i/o1 (so), i/o0 (si) qor 6b quad output read - command and address sent on single si line, data on quad output lines i/o3 (reset ), i/o2 (wp ), i/o1 (so), i/o0 (si) qior eb quad i/o read - command sent on si ngle si line, address input a nd data output on qu ad output lines i/o3 (reset ), i/o2 (wp ), i/o1 (so), i/o0 (si ). this opcode executes in extended spi ( quad i/o) sdr and in qpi sdr mode table 35. memory read command details opcode (hex) address length spi bus interface data transfer xip memory latency max clock frequency spi dual data quad data dual i/o quad i/o dpi qpi sdr execute- in-place dummy cycles 03 3 bytes yes na yes yes yes na yes 108 mhz 0b 3 bytes yes na yes yes yes yes yes 108 mhz 3b 3 bytes na yes na yes yes yes 108 mhz bb 3 bytes na yes na yes yes yes 108 mhz 6b 3 bytes na yes na yes yes yes 108 mhz eb 3 bytes na yes na yes yes yes yes 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 44 of 90 memory read (read, 03h) the read instruction reads out the memory contents at the given address. the address can start at any byte location of th e 4-mbit memory array determined by the three-byte address. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire 4-mbit memory can therefore be read out with one single read opcode and address provided. when the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. this command execu tes in spi, dpi, or qpi modes. note: the dummy cycles are a configurat ion option th rough the memory latency code bits (mlc0 to mlc3) in cr1. figure 47. read in spi mode figure 48. re ad in dpi mode figure 49. read in qpi mode 0 0 1 1 a23 a22 a1 a0 opcode (0 3h) address (3 bytes) read data dummy cycles d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z dm1 dm6 dm0 dm7 x x cs sck si (io0) so (io1) 0 0 0 0 0 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opcode (03h) address 3 bytes read data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 0 0 0 0 0 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opc. (03h) address 3 bytes read data d7 d6 d5 d4 d3 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d3 d2 d1 d0 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 45 of 90 fast read (fast_read, 0bh) the fast_read instruction reads out the memory contents at the given address. the address ca n start at any byte location o f the 4-mbit memory array determi ned by the three-byte address. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefor e be read out with one single read opcode and address provided. when the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. this command executes in spi, dpi or qpi modes. mode bits allow a series of fast read instructions to eliminate the 8-bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), significantly reduces initial access times (improves per for- mance). the mode bits control the length of the next fast_read operation through the inclusion or exclusion of the first byte instruction opcode . if the mode bits are axh the dev ice transitions to continuous fast_read mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the 0bh opcode thus elimi- nating 8 cycles from the inst ruction sequen ce. otherwise, opcode is required once cs transitions from high to low. notes: mode bits with !axh ( logical not of axh b yte) will exit the fast_read xip mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 50. fast_read in spi mode figure 51. fast_read in dpi mode 0 0 1 1 a23 a22 a1 a0 opcode (0bh) address (3 bytes) read data dummy cycles d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z dm1 dm6 dm0 dm7 x x cs sck si (io0) so (io1) mode byte m1 m6 m0 m7 0 0 0 0 1 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opcode (0bh) addr ess 3 bytes read data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si ( io0) so ( io1) mode byte m2 m4 m0 m6 m3 m5 m1 m7 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 46 of 90 figure 52. fast_read in qpi mode 0 0 0 0 1 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opc. (0bh) address 3 bytes read data d7 d6 d5 d4 d3 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) mode byte m2 m4 m0 m6 m3 m5 m1 m7 d3 d2 d1 d0 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 47 of 90 dual output read (dor , 3bh) the dor instruction is used in dual data mode which is the part of extended spi read instructions. in dual data mode, opcode, address, and mode byte (axh) and dummy cycles are trans- mitted through si pin, one bit p er clock cycle. at the falling edge of sck of the last dummy cycle, the pins are reconfigured as so becoming i/o1, and si becoming i/o0. the data (d7Cd0) from the specified address is shifted out on i/o1, and i/o0 pins two bits per clock cycle starting wit h d7 on i/o1, and d6 on i/o. t he address can start at any byte location of the memory array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out. when the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. mode bits allow a series of dor instruction to eliminate the 8- bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this featur e, called execute-in-place (xip), significantly reduces init ial access times (improves xip performance). the mode bits contr ol the length of the next dor operation through the inclusion or exclusion of the first byte instruction opcode. if the mode bits are axh, the device transi - tions to continuous dor mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the 3bh opcode thus eliminating eight cycles from the instruction sequence. otherwise, opcode is required once cs transitions from high to low. notes: mode bits with !axh (logical no t of axh byte) will exit the dor xip mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 53. double output read (dor) dual i/o read (dior , bbh) the dior instruction is used in dual addr/data mode which is part of extended spi read instructions. in dual addr/data mode, opcode is transmitted through si pin, one bit per clock cycle. after the last bit of the opcode, the pins are reconfigured as so becoming i/o1, and si becoming i/o0. the address is then transmitted into the part through i/o1 and i/o0 pins, 2 bits pe r clock cycle, starting with addres s a23 on i/o1 and a22 on i/o0, until the three-byte address is input. the data (d7Cd0) at the specific address is shifted out on i/o1, and i/o0 pins two bits per clock cycle starting with d7 on i/o1, and d6 on i/o0. the addre ss is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the en tire memory can, therefore, be read out. when the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. mode bits allow a series of dior instruction to eliminate the 8 -bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this featur e, called execute-in-place (xip), significantly reduces init ial access times (improves xip performance). the mode bits control the length of the next dior operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous dior mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the bbh opcode thus eliminating eight cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: mode bits with !axh ( logical not of axh b yte) will exit the fast_read xip mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 54. double i/o read (dior) 0 0 1 1 a23 a22 a1 a0 opcode (3bh) addr ess (3 bytes) read data (n bytes) mode byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z m1 m6 m0 m7 cs sck si (io0) so (io1) dummy cycles dm1 dm6 dm0 dm7 1 0 1 1 opcode (bbh) read data (n bytes ) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 mode byte a23 a22 a21 a20 a3 a2 a1 a0 address (3 bytes) hi-z hi-z hi-z hi-z m2 m4 m0 m6 m3 m5 m1 m7 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 cs sck si (io0) so (io1)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 48 of 90 quad output read (qor , 6bh) the qor instruction is used in quad data mode which is the part of extended spi read instructions. in quad data mode, opcode, address, mode byte (axh) and dummy cycles are transmitted through si pin, one bit per clock cycle. at the falling edge of sck of the last mode cycle, the p ins are reconfigured as reset becoming i/o3, wp becoming i/o2, so becoming i/o1, and si becoming i/o0. the dat a (d7Cd0) from the sp ecified address is shifted out on i/o3, i/o2, i/o1, and i/o0 pins four bits per cl ock cycle starting with d7 on i/o3 and d6 on i/o2, d5 on i/o1, and d4 on i/o0. the address is automatically incremented to the nex t higher address in sequential order after each byte of data is shifted out. the entire memory can, therefore, be read out. whe n the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. mode bits allow a series of dor instruction to eliminate the 8- bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this feat ure, called execute-in-place (xip), significantly reduces init ial access times (improves xip performance). the mode bits control the length of the next qor operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous qor m ode and the next addre ss can be entered (after cs is raised high and then asserted low) without requiring the 6bh opcode thus e liminating eight cycles from the instruction sequence. otherwis e, opcode is required once cs transitions from high to low. notes: the quad bit cr1[1] must be se t to 1 in the configuration register 1. mode bits with !axh (logical no t of axh byte) will exit the dor xip mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 55. quad output read (qor) 0 0 1 1 a23 a22 a1 a0 opcode (6bh) address (3 bytes) read data (n bytes) mode byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x hi -z hi -z hi -z hi-z hi-z hi-z hi-z m1 m6 m0 m7 cs sck si (io0) so (io1) wp (io2) reset (io3) dummy cycles dm1 dm6 dm0 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 49 of 90 quad i/o read (qior, ebh) C in extended spi mode the qior instruction is used in quad addr/data mode which is part of extended spi read instructions. in quad addr/data mode, opcode is transmitted through si pin, one bit per clock cycle. after the last bit of the opcode, the pins are reconfigu red as reset becoming i/o3, wp becoming i/o2, so becoming i/o1, and si becoming i/o0. the address is then transmitted int o the part through i/o3, i/o2, i/o1 and i/o0 pins, 4 bits per clo ck cycle, starting with address a23 on i/o3, a22 on i/o2, a21 on i/o1 and a20 on i/o0, until the three-byte address is input. th e data (d7Cd0) at the specific address is shifted out on i/o3, i/ o2, i/o1, and i/o0 pins four bits per clock cycle starting with d7 on i/o3 and d6 on i/o2, d5 on i/o1, and d4 on i/o0. the entire memory can therefore be read out. when the highest address 0x7ffff is reached, the address counter will wrap around and roll back to 0x000000, allowing the read sequence to continue indefinitely. mode bits allow a series of qior instruction to eliminate the 8 -bit opcode after the first instruction sends an axh mode bit (1010xxxx) pattern. this featur e, called execute-in-place (xip), significantly reduces init ial access times (improves xip performance). the mode bits contr ol the length of the next qior operation through the inclusion or exclusion of the first byte instruction opcode. if the mode b its are axh the device transit ions to continuous qior mode and the next address can be entered (after cs is raised high and then asserted low) without requiring the ebh opco de thus eliminating 8 cycles from the instruction sequence. otherwis e, opcode is required once cs is raised high and then asserted low. notes: the quad bit cr1[1] must be set to 1 in configuration register 1. mode bits with !axh (logical not of axh byte) will exit the qio r xip mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 56. quad i/o read (qior) in extended spi mode 1 1 1 1 opcode (ebh) read data (n bytes) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a23 a22 a21 a20 a3 a2 a1 a0 address (3 bytes) mode byte hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z m2 m4 m0 m6 m3 m5 m1 m7 cs sck si (io0) so (io1) wp (io2) reset (io3) dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 50 of 90 quad i/o read (qior, ebh) C in qpi mode the opcode for qior can be executed in the qspi mode as well. as the device is in qspi mode, the opcode, address, and mode bytes are transmitted over all four i/os. the data (d7Cd0) at t he specific address is shifted out on i/o3, i/o2, i/o1, and i/o0 p ins four bits per clock cycle starting with d7 on i/o3 and d6 on i/ o2, d5 on i/o1, and d4 on i/o0. notes: mode bits with !axh (logical not of axh byte) will exit the qio r mode. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. figure 57. quad i/o read (qior) in qpi mode 1 1 1 1 opc . (ebh ) read data (n bytes ) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a23 a22 a21 a20 a3 a2 a1 a0 address (3 bytes) mode byte hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z m2 m4 m0 m6 m3 m5 m1 m7 cs sck si (io0) so (io1) wp (io2) reset (io3) dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 1 1 1 1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 51 of 90 special sector memory the cy15x104qsn also provides an additional special sector memory region that is 256 bytes in length. this special sector region design for a higher thermal reliability for stored conte nt. data stored into this special sector can survive up to three standard reflow cycles. this spec ial sector locat ion can be use d to store the pcb module details, serial number details, and so on. the special sector memor y access commands support the spi, dpi, and qpi modes of operation. table 36. special sector memory access commands command opcode (hex) command description sswr 42 special sector write - ded icated command t o write 256 byt es special sector memory ssrd 4b special sector read - dedi cated command to read 256 bytes from the special sector memory table 37. special sector memory access command details opcode (hex) address length spi bus interface data transfer memory latency xip max clock frequency spi dual data quad data dual i/o quad i/o dpi qpi sdr dummy cycles execute- in-place 42 yes na yes yes yes na na 108 mhz 4b yes na yes yes yes yes na 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 52 of 90 special sector write (sswr, 42h) the special sector write operation is preformed when the sswr opcodes along with write data are given on the si pin for spi mode or the i/o1, i/o0 pins for dual mode (dpi) or the i/o3, i/ o2, i/o1, and i/o0 pins for quad mode (qpi). burst writes can be used to write consecutive addresses without issuing a new sswr instruction. if only one byte is to be written, the cs pin must be driven high after the d0 (lsb of data) is transmitted. however, if more bytes are to be written, the cs pin can be held low and the address is incremented automatically. the data bytes on the input pin(s) are written in successive addresses. address wrap is not supported in sswr. once the internal address counter auto increments to 0xff, cs should toggle high to terminate the ongoing sswr operation. data is written msb first. the rising edge of cs terminates a write operation. notes: the three-byte address contains the lower 8-bit for sector address (a7Ca0). while the remaining 16 most significant bits of the three-byte addre ss should be set to 0. sswr instruction can only be ex ecuted by the device if the write enable latch (wel) in sr1 is set to 1 to enable write operations. the wel bit of sr1 (sr1[1]) is automatically cleared to 0 aft er sswr command is terminated ( at the rising edge of cs ). figure 58. special sector write (sswr) in spi mode (wren is no t shown) figure 59. special sector write (sswr) in dpi mode (wren is no t shown) figure 60. special sector write (sswr) in qpi mode (wren is no t shown) 0 1 0 0 0 0 1 0 opcode (42h) address (3 bytes) a23a22a21d4a3a2a1a0 hi-z hi-z x x cs sck si (io0) so (io1) d7 d6 d5 d4 d3 d2 d1 d0 write data 0 1 0 0 0 0 1 0 opcode (42h) address (3 bytes) a23 a22 d5 d4 a3 a2 a1 a0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) d7 d6 d5 d4 d3 d2 d1 d0 write data 0 1 0 0 0 0 1 0 opc . (42h) address (3 bytes) a23 a22 a21 a20 a3 a2 a1 a0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d7 d6 d5 d4 d3 d2 d1 d0 write data
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 53 of 90 special sector read (ssrd, 4bh) the ssrd instruction reads out the memory contents at the given address. the address can start at any byte location of th e 256-byte special sector memory determined by the three-byte address. the address is automatic ally incremented to the next higher address in sequential order after each byte of data is shifted out. the entire 256-byte special sector can therefore b e read out with one single special sector read opcode and address provided. address wrap is not supported in ssrd. once the internal address counter auto increments to 0xff and if the hos t continues clocking on sck, the device will return undefined dat a byte(s). notes: the three-byte address contains the lower 8-bit for sector address (a7Ca0). while the remaining 16 most significant bits of the three-byte addre ss should be set to 0. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. the special sector f-ram guarantees to retain user data up to three cycles of standard reflow soldering. figure 61. special sector read (ssrd) in spi mode figure 62. special sector read (ssrd) in dpi mode figure 63. special sector read (ssrd) in qpi mode 0 0 1 1 a23 a22 a1 a0 opcode (4bh) address read data dummy cycles d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z dm1 dm6 dm0 dm7 x x cs sck si (io0) so (io1) hi-z 0 1 0 0 1 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opcode (4bh) address read data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 0 1 0 0 1 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opc. (4bh) address read data d7 d6 d5 d4 d3 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) d3 d2 d1 d0 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 54 of 90 error correction code (ecc) and cyclic redundancy check error correction code (ecc) the cy15x104qsn provides an in-built hardware error correction code (ecc) with 2-bit error detection and reporting on an 8-byte (64 bits) unit data. since every f-ram read follow s a write cycle (refresh cycle), th e 1-bit error de tected is auto mat- ically corrected and written back to the f-ram array during the refresh cycle. hence, cy15x104qsn does not report 1-bit error detection because the subsequent ecc check on the same data unit will not reproduce the same 1-bit error. cy15x104qsn ecc is always enabled and observes the following behavior in run time: whenever there is a 2-bit error detected during f-ram read, cy15x104qsn will set the ecc status register (eccsr) 2bd flag bit to 1 (eccsr is cleared after por, reset, or clecc) and also captures the corresponding unit data address in the 4-byte addrtrap register. the first three ls bytes of addrtrap register will hold the 3-byte unit data address of the very first 2-bit error detected after por, reset, or clecc. any subsequent occurrence of a 2-bit error will not overwrite the addrtrap register with the most recent data unit address. cy15x104qsn provides a 2-byte ecc detection count (eccdc) register which increments by 1 every time a 2-bit error is detected. the eccdc register is cleared after por, any reset event, or after clecc command execution. user can read either addrtrap r egister for its non-zero value (with an exception to where the 2-bit error detected at address 0x00000) or read 2bd flag bit of eccsr register, or read the non-zero value in the eccdc register to determine the occur- rence of a 2-bi t error detection. in addition, cy15x104qsn also supports the eccrd (19h) command which returns the 2-bit error detection status in 8-byte unit data by setting the 2bd error flag to 1 in the eccsr at the unit address s ent with the eccrd command. ecc is not supported on the 256-byte special sector memory, status and configuration registers. ecc status register the status of ecc is presented in the ecc status register (eccsr). the eccsr details are shown in ta b l e 3 9 . the eccsr content can be read only by using the rdar commands as described in section read any register (rdar, 65h) . the eccrd command returns the eccsr status for the unit data. the unit data is defined as the number of bytes over which the ecc is calculated. cy15x104q sn has 8-bytes unit data. 2-bit ecc detection (2bd) eccsr [4]: this bit indicates that a 2-bit ecc detection has occurred on t he read data since the last clear ecc status register. the clecc instruction resets 2bd bit to 0. ecc detection counter (eccdc) the ecc detection counter (eccdc) register is a 2-byte volatile register, which stores the number of times 2-bit error detections have occurred during the memory read operations since the last por, any reset e vent, or after clecc command. the eccdc register content can be read by using rdar commands as described in section read any register (rdar, 65h) . notes: once the eccdc count reaches 0xffff, the eccdc will stop incrementing. the eccdc loses its content when in deep power-down (dpd) mode and returns with 0x0000 upon dpd exit. table 38. ecc status register eccsr[7] eccsr[6] eccsr[5] eccsr[4] eccsr[3] eccsr[2] eccsr[1] eccsr[0] rfu (0) rfu (0) rfu (0) 2bd (0) rfu (0) rfu (0) rfu (0) rfu (0) table 39. ecc status register details bit bit name bit function type read/write description eccsr[7] rfu reserved (0) reserved for future use eccsr[6] rfu reserved (0) reserved for future use eccsr[5] rfu reserved (0) reserved for future use eccsr[4] 2bd 2-bit ecc detection v r 1 = 2-bit error detection occurred since last eccsr clear com mand (clecc) 0 = 2-bit error detection has not occurred since last eccsr cle ar command (clecc) eccsr[3] rfu reserved (0) reserved for future use eccsr[2] rfu reserved (0) reserved for future use eccsr[1] rfu reserved (0) reserved for future use eccsr[0] rfu reserved (0) reserved for future use v - volatile
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 55 of 90 address trap register (addtrap) the address trap register (addtrap) is a 4-byte volatile register which stores the ecc unit data address where a 2-bit error detection has occurred during a read operation. the addtrap register stores the address of very first ecc data unit in which 2-bit error detected since the last clear ecc instruct ion (clecc), por, or any reset ev ent. the address of subsequent data unit with 2-bit error detected will not be captured into addtrap. in this case only eccdc count will increment. the addtrap register content can be read by using the rdar command as described in section read any register (rdar, 65h) . note: the addtrap register loses its content when in deep power down (dpd) mode and returns with 0x00000000 upon dpd exit. ecc commands the cy15x104qsn ecc commands are described in the following sec tion. ecc status read (eccrd, 19h) the eccrd instruction is used to determine the 2-bit error detection status of the addressed unit data. to do so, cs is pulled low and the eccrd instruction is followed by the ecc data unit address in which the three least significant bits (lsb) of address should be set to zero. e ven if the least three signific ant bits (lsb) of address are not set to zero, they will be ignored internally and the start address for the data unit is determine d by the rest of t he ms bits. the address bytes are followed by the number of dummy cycles selected by the read latency value for the memory read. the 8-b it ecc status is shifted out on output lines. cs must be pulled high after 8-bit ecc status is read out. notes: if cs remains low after 8-bit ecc status is read out, the subse- quent ecc status data will be indeterminate. it is necessary to send the new eccrd command with next unit address to read the ecc status of next data unit. the dummy cycles are a configu ration option through the memory latency code bits ( mlc0 to mlc3) in cr1. table 40. ecc detection counter register (eccdc) bits name function type read/write default state description 15:0 eccdc ecc 2-bit error detection count v r 0x0000 total count of 2-bit ecc detections since the last por or any reset event. clecc co mmand does not clear this register. v - volatile table 41. address trap register bits name function type read/write default state description 31:0 addtrap stores ecc address v r 0x00000000 store address of unit data where 2-bit ecc detection occurred v - volatile table 42. ecc commands command (hex) opcode command description eccrd 19 ecc status read - determi nes the ecc status of the addre ssed unit data clecc 1b clear ecc register (s) - ecc flags and address trap regi sters table 43. ecc command details opcode (hex) address length spi bus interface data transfer memory latency xip max clock frequency spi dual data quad data dual i/o quad i/o dpi qpi sdr dummy cycles execute -in-place 19 3 bytes yes na yes yes yes yes na 108 mhz 1b na yes na yes yes yes na na 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 56 of 90 figure 64. ecc read (eccrd) in spi mode figure 65. ecc read (eccrd) in dpi mode figure 66. ecc read (eccrd) in qpi mode table 44. unit data ecc status byte bits name function read/write default state description 7 rfu reserved 0 reserved for future use 6 rfu reserved 0 reserved for future use 5 rfu reserved 0 reserved for future use 4 rfu reserved 0 reserved for future use 3 eecc2d 2-bit error in ecc unit r 0 1 = 2 bit error detected in ecc unit 0 = no error 2 rfu reserved 0 reserved for future use 1 rfu reserved 0 reserved for future use 0 rfu reserved 0 reserved for future use 0 0 0 1 a23 a22 a1 a0 opcode (19h) address (3 bytes) ecc read data dummy cycles d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z dm1 dm6 dm0 dm7 x x cs sck si (io0) so (io1) 0 0 0 1 1 0 1 1 a23 a22 a21 a20 a3 a2 a1 a0 opcode (19h) address (3 bytes) ecc read data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 0 0 0 1 1 0 0 1 a23 a22 a21 a20 a3 a2 a1 a0 opc. (19h) address (3 bytes ) ecc read data d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) dummy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 57 of 90 clear ecc (clecc, 1bh) the clecc instruction clears all ecc flags, addtrap, and eccdc registers. it is not necessary to set the wel bit before a clecc instruction is executed. figure 67. clear ecc (clecc) in spi mode figure 68. clear ecc (clecc) in dpi mode figure 69. clear ecc (clecc) in qpi mode cyclic redundancy check (crc) cy15x104qsn provides an in-built cyclic redundancy check (crc) engine that computes the check sequence on the stored data in the memory array. crc is not supported on 256-byte special sector memory, status and configurations registers. the cy15x104qsn supports crc with the following opcodes. opcode (1bh) hi-z hi-z x cs sck si (io0) so (io1) x 0 0 0 1 1 0 1 1 opcode (1bh) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 0 0 0 1 1 0 1 1 opc . (1bh) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) 0 0 0 0 0 1 1 0 table 45. crc access commands command opcode (hex) command description crcc 5b crc calculation - performs a crc calculation over a user defined address range epcs 75 crc suspend - interrupts t he crcc operation and allow oth er accesses epcr1 7a crc resume - resumes suspended crcc operation table 46. crc access command description opcode (hex) address length spi bus interface data transfer memory latency xip max clock frequency spi dual data quad data dual i/o quad i/o dpi qpi sdr dummy cycle execute -in-place 5b na yes na yes yes yes na na 108 mhz 75 na yes na yes yes yes na na 108 mhz 7a na yes na yes yes yes na na 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 58 of 90 data crc calculation (crcc, 5bh) the crcc instruction sequence causes cy15x104qsn to perform a cyclic redundancy check calculation (crcc) over a user-defined address range. a data crc-enabled cy15x104qsn device calcul ates a fixed-length binary sequence, known as the crc checksum, for each block of data and sends them both together to the host. when the host device receives the data block, it recalculates the crc checksum. if t he new crc checksum does not match the original checksum sent with the data, then the block contains a data error and the hos t device may take corrective action such as requesting the data block to be sent again. the crcc process calculates the check-value on the data contained at the starting addres s through the ending address. the crc calculation instruction starts by entering the opcode followed by the starting address and ending address. cs must be driven high after the ending address has been latched in. this will initiate the beginning of internal crc process that c alcu- lates the check-value on the data contained at the starting address through the ending address. if cs is not driven high after the last bit of address, t he crc calculation operation wi ll not be executed. the crcc command does not check the wel status. however, if the wel is set 1 prior to the crc command , the wel gets cleared to 0 after the crc operation is complete . the ending address (ea) should be at least a 32-bit aligned word higher than the starting address (sa). if ea < sa + 3, the crc calculation will abort and the device will return to the standby mode. the crc abort (crca) bit (sr2[3] = 1) is set to indicate the aborted condition and the crc register (crcr) will hold indete rminate data. when the crc calculation is in progress, cy15x104qsn sets the wip bit of sr1 (sr1[0]) to 1. user can poll the wip statu s to determine when the ongoing crcc operation is complete and device is ready for access. the wip bit will be 1 when the cr c calculation is in progress and a '0' when it has been completed . the crc register (crcr) stores t he results of the crc process that calculates the check-value on the data contained at the starting address through the ending address. the details of the crc register is described in table 47 . the crc check-value bits 0-31 can be read by reading the crc register using read any register (rdar) command as described in section read any register (rdar, 65h) . the crc register bits are initialized with all 0s (0x00000000) every time crc calculation is initiated. a por or any reset eve nt will also initialize the crc register value to all 1s. the check-value calculation can be suspended with the crc suspend command (epcs, b0h) t o read data from the memory array or registers. during the suspended state, the crc suspend (crcs) status bit in status register-2 will be set (sr2[4] = 1). once suspended, the host can read the status register, read data from the array and can resume the crc calculation by using the crc resume command (epcr, 30h). cy15x104qsn takes t crcc to calculate the crc checksum on data between the sa and ea (i ncluding data at sa and ea). the 32-bit crc (crc-32c) polynomial (0x1edc6f41) is defined as follows: 32x + 28x + 27x + 26x + 25x + 23x + 22x + 20x+ 19x + 18x + 14x + 13x + 11x + 10x + 9x + 8x + 6x + 1x note: 4-byte memory data are inte rnally read as {data[7:0], data[15:8], data[23: 16], data[31:24]} and are assigned to crc[31:0] for the crc calculation. figure 70. crc calculat ion (crcc) in spi mode table 47. crc register description bits name function read/write default state description 31:0 crcr check crc value r/w 0x00000000 store the check-valu e result from th e crc calculat ion command 0 1 0 1 1 0 1 1 opcode (5bh) start address (3 bytes) a23a22a21d4a3a2a1a0 hi-z hi-z x x cs sck si (io0) so (io1) a23a22a21d4a3a2a1a0 end address (3 bytes) t crcc
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 59 of 90 figure 71. crc calculat ion (crcc) in dpi mode figure 72. crc calculat ion (crcc) in qpi mode crc suspend (epcs, 75h) epcs allows the system to interrupt the ongoing crcc operation and allow other accesses while the current crc operation is suspended. commands which can execute while crc is suspended are: read, rdsr1, rdsr2, fast_read, eccrd, clecc, rdcr1, dor, rdcr2, rdcr4, ssrd, rdcr5, rdar, rsten, qor, epcr, rst, rdid, dior, rdsn, qior. the crc suspend is valid only during a crc calculation operation. the status register 2 (sr2) can be checked to determine if the crcc operation has been suspended or completed. the crc status bit shows if a crcc operation is suspended or was completed at the time wip status bit in status register 1 changes to 0. epcs takes t crcs time to process the crc suspend ope ration and keeps the wip bit status 1. in the case crcc calculation completes before the epcs command is fully processed, the crcs bit in sr2 (sr2 [4]) will not set to 1, indicating epcs did not execute. figure 73. crc suspend (epcs) in spi mode 0 1 1 0 1 0 1 1 opcode (5bh) start addr (3 bytes) a23 a22 a21 a20 d3 d2 a1 a0 hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) a23 a22 d5 d4 a3 a2 0 0 end addr (3 bytes) 0 1 0 1 1 0 1 1 opc. (5bh) start addr (3 bytes) a23 a22 a21 a20 d3 d2 d1 d0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) a3 a2 a1 a0 end addr (3 bytes) a23 a22 a21 a20 d3 d2 d1 d0 a3 a2 0 0 0 1 1 1 0 1 0 1 opcode (75h) hi-z hi-z x cs sck si (io0) so (io1) x t crcs
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 60 of 90 figure 74. crc suspend (epcs) in dpi mode figure 75. suspend (epcs) in qpi mode crc resume (epcr, 7ah) epcr resumes a suspended crcc operation. after the crc resume instruction is issued, the wip bit is set to 1. the cr cc operation can be interrupted as often as necessary. the epcr resumes a suspended crcc operation only when crcs bit of sr2 (sr2[4]) is set 1, otherwise epcr command will be ignored. after the epcr instruct ion is issued, the wip bit is s et to 1. the crcc operation can be interrupted and resumed as often as necessary. epcr takes t crcr time to process the command and resumes the crc calculation on the remaining data bytes, until the end address (ea) reaches. figure 76. crc resume (epcr) in spi mode figure 77. crc resume (epcr) in dpi mode figure 78. crc resume (epcr) in qpi mode 0 1 1 1 0 1 0 1 opcode (75h) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 0 1 1 1 0 1 0 1 opc . (75h) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) 0 1 1 1 1 0 1 0 opcode (7ah) hi-z hi-z x cs sck si (io0) so (io1) x t crcr 0 1 1 1 1 0 1 0 opcode (7ah) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 0 1 1 1 1 0 1 0 opc . (7ah) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 61 of 90 identification and serial number the cy15x104qsn device offers three different types of identi- fication features that include device id and unique id which ar e 8-byte read only registers and 8-byte writable serial number registers. details of each is d escribed in the following sectio n. read device id (rdid, 9fh) the cy15x104qsn device can be interrogated for its manufac- turer, product identification, and die revision. the rdid opcod e 9fh allows the user to read the 8-byte manufacturer id and product id, both of which are read-only bytes. the device id fi eld is described in the device id field register table. the device id of the corresponding part number is shown in the ordering infor- mation . notes: the dummy cycles shown are a configuration option through register latency code bi ts (rlc0, rlc1) in cr5. rdid data preference - lsb shifts out first, msb shifts out las t. no wrap is allowed for the rdid command. after the 8th byte, if the host continues to clock the device will r eturn undefined data byte/s. figure 79. read device id (rdid) in spi mode figure 80. read device id (rdid) in dpi mode table 48. device id field bits (number of bits) 63C32 (32 bits) 31C21 (11 bits) 20C8 (13 bits) 7C3 (5 bits) 2C0 (3 bits) description 00000000000000000000000000000000 (reserved) 00000110100 (manufacturer id) product id density id die rev 1 00 1 1 11 1 opcode (9fh) id data hi-z x dummy byte dm1 dm6 dm0 dm7 id7 id6 id1 id0 hi-z x id15 id14 id9 id8 id63 id62 id57 id56 byte 0byte 1byte 7 cs sck si ( io0) so ( io1) 1 0 0 1 1 1 1 1 opcode (9fh) id data hi-z hi-z cs sck si (io0) so (io1) id7 id6 d1 d0 hi-z hi-z id1 id0 id15 sn14 d1 d0 id9 id8 id63 id62 d1 d0 id57 id56 byte 0 byte 1 byte 7 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 62 of 90 figure 81. read device id (rdid) in qpi mode read unique id (ruid, 4ch) the cy15x104qsn device can be interrogated for its unique id which stores a unique number for each device. the ruid opcode 4ch allows the user to read the 8-byte unique id which are read-only bytes. the unique id is generate by combining details on fab lot number, wafer number, y-coordinate and x-coordinate of the die. notes: the dummy cycles shown are a configuration option through register latency code bi ts (rlc0, rlc1) in cr5. ruid data preference - lsb shifts out first, msb shifts out las t. no wrap is allowed for the rdid command. after the 8th byte, if the host continues to clock, the device will return undefine d data byte(s). the unique id registers guarantee to retain user data up to three cycles of standard reflow soldering. figure 82. read unique id in spi mode 1 0 0 1 1 1 1 1 opc. (9fh) id data hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) hold (io3) id7 id6 id5 id4 id3 id2 id1 id0 hi-z hi-z hi-z hi-z id3 id2 id1 id0 id31 id30 id29 id28 id27 id26 id25 id24 id63 id62 id61 id60 id63 id62 id61 id60 id59 id58 id57 id56 byte 0 byte 3 byte 7 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 table 49. 8-byte unique id fab lot wafer no y-coordinate x-coordinate 36-bits 8-bits 10-bits 10-bits 0 10 0 1 10 0 opcode (4ch) unique id hi-z x dummy byte cs sck si ( io0) so ( io1) dm1 dm6 dm0 dm7 id7 id6 id1 id0 hi-z x id15 id14 id9 id8 id63 id62 id57 id56 byte 0 byte 1 byte 7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 63 of 90 figure 83. read unique id in dpi mode figure 84. read unique id in qpi mode write serial number (wrsn, c2h) the serial number is an 8-byte programmable memory space provided to the user to uniquely identify a pc board or a syste m. a serial number typically consists of a two byte customer id, followed by five bytes of unique serial number and one byte of crc check. however, end application can define their own format for 8-byte serial number. all writes to the serial numbe r register begin with a wren opcode with cs being asserted and de-asserted. the next opcode is wrsn. the wrsn instruction can be used in burst mode to write all the 8 bytes of serial number. after the last byte of serial number is shifted in, cs must be driven high to comp lete the wrsn operation. notes: the wrsn instruction can only be executed by the device if the write enable latch (wel) in the status register is set to 1 to enable write operations . when the wrsn operation is completed, the write enable latch (wel) is reset to a '0'. wrsn data preference - lsb shifts in first, msb shifts in last. the crc checksum on the 7-byte id is no t calculated by the device. the system firmware must calculate the crc checksum and append the checksum to the 7-byte user defined serial number before programmi ng the entire 8-byte serial number into the serial number re gister. factory default value for the 8-byte serial nu mber is 0x0000000000000000. the wel bit is automatically cleared to 0 after wrsn command is terminated (at t he rising edge of cs ). exactly 8 bytes must be entered , otherwise the serial number write (wrsn) will not execute. 0 1 0 0 1 1 0 0 opcode (4ch) unique id hi-z hi-z cs sck si (io0) so (io1) id7 id6 d1 d0 hi-z hi-z id1 id0 id15 sn14 d1 d0 id9 id8 id63 id62 d1 d0 id57 id56 byte 0 byte 7 byte 7 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 0 1 0 0 1 1 0 0 opc. (4ch) unique id hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) hold (io3) id7 id6 id5 id4 id3 id2 id1 id0 hi-z hi-z hi-z hi-z id3 id2 id1 id0 id31 id30 id29 id28 id27 id26 id25 id24 id63 id62 id61 id60 id63 id62 id61 id60 id59 id58 id57 id56 byte 0 byte 7 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1 table 50. 8-byte serial number 16-bit customer identifier 40-bit unique number 8-bit crc sn[63:56] sn[55:48] sn[47:40] sn[39: 32] sn[31:24] sn[23:16] sn[15:8] s n[7:0]
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 64 of 90 figure 85. write serial number in spi mode (wren not shown) figure 86. write serial number in dpi mode (wren not shown) figure 87. write serial number in qpi mode (wren not shown) opcode (c2h) sn write data hi-z 1 1 0 0 0 0 1 0 x cs sck si (io0) so (io1) sn7 sn6 d4 sn1 sn0 hi-z x sn7 sn6 d4 sn1 sn0 sn7 sn6 d4 sn1 sn0 byte 0 byte 7 1 1 0 0 0 0 1 0 opcode (c2h) sn write data hi-z hi-z cs sck si (io0) so (io1) sn7 sn6 d5 d4 sn1 sn0 hi-z hi-z sn7 sn6 d5 d4 sn1 sn0 sn7 sn6 d5 d4 sn1 sn0 byte 0 byte 7 sn write data hi-z hi-z hi-z hi-z 1 1 0 0 0 0 1 0 opc. (c2h) cs sck si (io0) so (io1) wp (io2) reset (io3) sn7 sn6 sn5 sn4 sn3 sn2 sn1 sn0 hi-z hi-z hi-z hi-z sn15 sn14 sn13 sn12 sn 11 sn 10 sn9 sn8 sn63 sn62 sn61 sn60 sn59 sn58 sn57 sn56 byte 0 byte 7
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 65 of 90 read serial number (rdsn, c3h) the cy15x104qsn device incorporates an 8-byte serial space provided to the user to uniquely identify the device. the seria l number is read using the rdsn instruction. a serial number read may be performed in burst mode to read all the eight bytes at once. after the last byte of serial number is read, the device loops back to the first (msb) byte of the serial number. an rdsn instruction can be issued by shifting the opcode for rdsn after cs goes low. notes: the dummy cycles shown are a configuration option through register latency code bi ts (rlc0, rlc1) in cr5. rdsn data preference - lsb shif ts out first, msb shifts out last. no wrap is allowed for the rdid command. after the 8th byte, if the host continues to clock the device will return undefined data byte/s. figure 88. read serial number (rdsn) in spi mode figure 89. read serial number (rdsn) in dpi mode figure 90. read serial number (rdsn) in qpi mode 1 10 0 0 01 1 opcode (c3h) sn read data hi-z x dummy byte cs sck si ( io0) so ( io1) dm 1 dm6 dm 0 dm 7 sn7sn6 sn1sn0 hi-z sn15 sn14 sn 9 sn 8 sn63 sn62 sn57 sn56 byte 0 byte 1 byte 7 1 1 0 0 0 0 1 1 opcode (c3h) sn read data hi-z hi-z cs sck si (io0) so (io1) sn 7 sn 6 d1 d0 hi-z hi-z sn 1 sn 0 sn15 sn14 d1 d0 sn 9 sn 8 sn63 sn62 d1 d0 sn57 sn56 byte 0 byte 7 byte 7 dummy cycles dm6 dm7 dm1 dm0 dm1 dm0 dm6 dm7 1 1 0 0 0 0 1 1 opc. (c3h) sn read data hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) hold (io3) sn 7 sn 6 sn 5 sn 4 sn 3 sn 2 sn 1 sn 0 hi-z hi-z hi-z hi-z sn 3 sn 2 sn 1 sn 0 sn31 sn30 sn29 sn28 sn27 sn26 sn25 sn24 sn63 sn62 sn61 sn60 sn63 sn62 sn61 sn60 sn59 sn58 sn57 sn56 byte 0 byte 7 dmy cycles dm6 dm7 dm6 dm7 dm6 dm7 dm6 dm7 dm0 dm1 dm0 dm1 dm0 dm1 dm0 dm1
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 66 of 90 low power modes and resets table 51. low power mode and reset commands command opcode (hex) command description dpd b9 deep power down - enter s deep-power-down power mode hbn ba hibernate mode - ent ers hibernate power mode rsten 66 reset enable - pre comm and to enable software reset rst 99 software reset - command to initiate software reset table 52. low power mode an d reset command description opcode (hex) address length spi bus interface data transfer latency (none) xip max clock frequency spi dual data quad data dual i/o quad i/o dpi qpi sdr dummy cycles execute -in-place b9 na yes na yes yes yes na na 108 mhz ba na yes na yes yes yes na na 108 mhz 66 na yes na yes yes yes na na 108 mhz 99 na yes na yes yes yes na na 108 mhz
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 67 of 90 deep power-down mode (dpd, b9h) the device enters deep power down mode when the dpd opcode bah is clocked in and a rising edge of cs is applied. when in deep power-down mode, the sck and si pins are ignored and so goes to hi-z, but the device continues to monito r the cs pin. a cs pulse-width of t csdpd or hardware reset exits the dpd mode after t extdpd time. the cs pulse-width can be generated either by sending a dummy command cycle or toggling cs alone while sck and i/os are dont care. the i/os remain in hi-z stat e during the wakeup from deep power down. refer to figure 91 for dpd entry and figure 94 for dpd exit timing. notes: the timing details shown in the figure 91 are applicable as is in dpi and qpi modes. crc register (crcr) and ecc registers (eccdc and addrtrap) will lose their cont ent in the dpd mode and will return to their default values, 0x00. the wel bit (sr0[1]) status is not retained in the dpd mode. if the wel status was '1' before entering dpd, it will clear to '0' after the dpd mode exits. figure 91. dpd entry in spi mode figure 92. deep power-down mode operation in dpi mode figure 93. deep power-down mode operation in qpi mode figure 94. dpd exit in spi mode 012345 67 1 0 0 1 1 1 0 1 cs sck si so hi-z opcode (b9h) enters deep-power-down mode t entdpd 1 0 1 1 1 0 0 1 opcode (b9h) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 1 0 1 1 1 0 0 1 opc . (b9h) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) i/os x 012 cs sck t extdpd t csdpd t su
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 68 of 90 hibernate mode (hbn, bah) the device enters hibernate mode when the hbn opcode b9h is clocked in and a rising edge of cs is applied. when in hibernate mode, the sck and si pins are i gnored and so will be hi-z, but the device continues to monitor the cs pin. on the next falling edge of cs , the device will return to normal operation within t exthib time. the so pin remains in a hi-z state during the wakeup from hibernate period. the device does not necessarily respond to an opcode within t he wakeup period. to exit the hibernate mode, the controlle r may send a dummy read, for example, and wait for the remaining t exthib time. notes: the timing details shown in the spi mode timing diagram are applicable as is in th e dpi and qpi modes. return from hibernate reloads all registers to their default po r values. refer to table 2 on page 10 for details on registers default values after por. figure 95. hibernate mode operation in spi mode figure 96. hibernate mode operation in dpi mode figure 97. hib ernate mode operation in qpi mode 012345 67 0 1 0 1 1 1 0 1 cs sck si so hi-z opcode (bah) enters hibernate mode 012 t exthib recovers from hibernate mode t su t enthib 1 0 1 1 1 0 1 0 opcode (bah ) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 1 0 1 1 1 0 1 0 opc . (bah ) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3)
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 69 of 90 software reset the software reset operation combines two instructions: reset-enable (rsten) instruction followed by a reset (rst) instruction. it resets the whole device and makes it ready to receive instructi ons only after t sreset time. notes: any instruction other than rst following the rsten instruction will clear the reset enable condition and prevent a later rst instruction from being recognized. during software reset, only rdsr1 and rdar (to access rdsr1) commands are support ed. other commands will be ignored. the timing details shown in the spi mode timing diagram are applicable as is in th e dpi and qpi modes. figure 98. software reset timing in spi mode figure 99. software reset timing in dpi mode figure 100. software reset timing in qpi mode 0 1 1 0 0 1 1 0 opcode (66h) hi-z x x cs sck si (io0) so (io1) 1 0 0 1 1 0 0 1 opcode (99h) hi-z x x hi-z software reset starts t sreset t cs 0 1 1 0 0 1 1 0 opcode (66h) hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) 1 0 0 1 1 0 0 1 opcode (99h) hi-z hi-z 0 1 1 0 0 1 1 0 opc. (66h) hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z cs sck si (io0) so (io1) wp (io2) reset (io3) 1 0 0 1 1 0 0 1 opc. (99h) hi-z hi-z hi-z hi-z
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 70 of 90 hardware reset (reset ) the hardware reset input (reset ) is multiplexed on (reset / (i/o3) and is an active low signal in cy15x104qsn device. refer to ta b l e 1 6 for hardware reset (reset ) pin configurations across various spi interfaces. when reset is pulled low, cy15x104qsn self initializes and brings its configuration back to the power up status. refer to ta b l e 5 3 for different registers configuration after reset cycle. once reset is issued, cy15x104qsn takes t rph /t hreset time from reset rising edge to complete the reset cycle. cy15x104qsn becomes inaccessible during t rph time. figure 101 to figure 103 show the reset timings in differ ent reset mode. notes: the reset pin is multiplexed on i/o3 in the qpi mode. when using the hardware (reset ) in qpi mode, the cr2 [5] bit must be set to 1 to enable to use i/o3 as reset input when cs is high. figure 101 shows the reset / (i/o3) timing in qpi mode quad bit cr1 [1] in configuration register 1 must be set to 0 to enable the hardware reset feature on the reset pin. the reset signal has an internal pull-up resistor and may be left unconnected if not used. this pull-up resistor gets disabl ed when the pin is configured as i/o3. reset signal should never be tied low even if reset function- ality is disabled since it will increase leakage current due to the internal weak pull-up. in a shared bus configurati on in qpi mode, if the reset function is enabled, the device will reset every time (reset / (i/o3)) toggles due to any ongoing communication between the master another qspi slave on the same bus. hence, it is recommended to disable reset pin functionality in a shared bus configuration. figure 101. reset timing - spi with quad set (cr1 [1]= 1) or qpi enabled (cr2[6 ] = 1) figure 102. reset timing - spi with quad clear (cr1[1]= 0) and qpi disabled (c r2[6] = 0) cs reset t rs t rp t rph /t hreset cs reset t rp t rph /t hreset t rph /t hreset t rp reset new reset dont care
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 71 of 90 jedec spi reset jedec spi reset is a signaling protocol which initiates a hardw are reset independent of the devices operating i/o mode. it br ings the device to its default mode as selected in the status and config uration registers. table 53 on page 72 shows the device status after the default recovery is initiated. the default recovery steps are as follows: 1. cs toggles active low to select the spi slave. 2. sck remains stable either i n a high or in a low state. 3. si (i/o0) toggles high to low, simultaneously with cs going low. other i/os (i/o1, i/o2 , and i/o3) remain dont care . 4. cs is driven high while i/o0 remain low. 5. repeat the above steps 1 to 4 e ach time alternating the state of si (i/o0) at the falling edge of cs for a total of four times. 6. reset occurs after the 4 th cs goes high (inactive). refer to figure 103 for timing details. figure 103. jedec spi reset hi-z cs sck si (io0) so (io1) sck @ 1 - mode 3 sck @ 0 - mode 0 t csl t csh_r t su t hd_r t hreset start next valid access
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 72 of 90 the spi host can issue hardware reset or jedec spi reset if cy15x104qsn goes into an undefined state and stops responding to any spi command. the cy15x104qsn enters into an internal test mode or any undefined mode either due to wrong opcode or any glitch on the spi signals which can inter- nally cause latching of a wrong opcode, or part didnt boot up successfully (keep showing bu sy status wip = 1 after t pu ). note: ecc (eccdc and addrtrap) registers lose their content while in dpd and return to their default values 0x00 fo r ecc registers. return from hiber nate reloads all registers to t heir default values at pow er up as shown in table 2 on page 10 . table 53. status of registers after various types of reset reset function i/o requirements status registers (srx) configuration register (crx) ecc status crc reg ecc count reg (eccdc) addr trap reg (addtrap) i/o modes power-on reset cs = 1 other inputs - ignored all outputs - tristated sr1 - no change sr2 - 0x00 cr1, cr2, cr4, cr5 load default values load - 0x00 load - 0x00 load - 0x00 load - 0x00 no change hardware reset cs = 1 other inputs - ignored all outputs - tristated sr1 - no change sr2 - 0x00 cr1, cr2, cr4, cr5 load default values load - 0x00 load - 0x00 load - 0x00 load - 0x00 no change software reset instruction (rsten, rst) sr1 - no change sr2 - 0x00 cr1, cr2, cr4, cr5 load default values load - 0x00 load - 0x00 load - 0x00 load - 0x00 no change jedec reset (default recovery) cs and si (io0) = toggle other inputs - ignored all outputs - tristated sr1 - no change sr2 - 0x00 cr1, cr2, cr4, cr5 load default values load - 0x00 load - 0x00 load - 0x00 load - 0x00 no change
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 73 of 90 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ............................... C55 c to + 125 c maximum accumula ted storage time at 125 c ambient temperature ................................. 1000 h at 85 c ambient temperature ............................... 10 years maximum junction temperature ................................ 1 25 c supply voltage on v dd relative to v ss : cy15v104qsn: ..........................................C1.0 v t o +2.4 v CY15B104QSN: ..........................................C1.0 v t o +4.1 v input voltage ............................................ v in ? v dd + 1.0 v dc voltage applied to outputs in high-z state ................................... C1.0 v to v dd + 1.0 v transient voltage (< 20 ns) on any pin to ground potential ............ C2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ..................................................... ............ 1.0 w surface mount lead soldering temperature (3 seconds) .......................... +26 0 c dc output current (1 output at a time, 1s duration) .... 15 ma electrostatic discharge voltage human body model (jedec std jesd22-a114-b) ...... 2 kv charged device model (jedec std jesd22-c101-a) ..................................... 500 v latch-up current .............................................. ....... >140 ma operating range device ambient temperature v dd cy15v104qsn industrial, C40 c to +85 c 1.71 v to 1.89 v CY15B104QSN 1.8 v to 3.6 v dc electrical c haracteristics over the operating range parameter description test conditions min typ [13] max unit v dd power supply cy15v104qsn 1.71 1.8 1.89 v CY15B104QSN 1.8 3.0 3.6 v i dd1 v dd supply current in spi sdr mode v dd = 1.71 v to 1.89 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 50 mhz C 4.5 5.2 ma f sck = 108 mhz C 10 12 ma v dd = 1.8 v to 3.6 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 50 mhz C 5.2 6.6 ma f sck = 108 mhz C 11 14 ma i dd2 vdd supply current in dpi sdr mode v dd = 1.71 v to 1.89 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 108 mhz C 12 14 ma v dd = 1.8 v to 3.6 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 108 mhz C 13 16 ma note 13. typical values are at 25 c, v dd = 3.0 v. not 100% tested.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 74 of 90 i dd3 v dd supply current in qpi sdr mode v dd = 1.71 v to 1.89 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 108 mhz C 16 19 ma v dd = 1.8 v to 3.6 v; sck toggling between v dd C 0.2 v and v ss , other inputs v ss or v dd C 0.2 v. no output loads. f sck = 108 mhz C 17 21 ma i sb v dd standby current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 102 C a t a = 85 oc C C 209 a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 165 C a t a = 85 oc C C 350 a i dpd deep power-down current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 0.70 C a t a = 85 oc C C 15 a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 1.0 C a t a = 85 oc C C 17 a i hbn hibernate mode current v dd = 1.71 v to 1.89 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 0.1 C a t a = 85 oc C C 0.9 a v dd = 1.8 v to 3.6 v; cs = v dd . all other inputs v ss or v dd . t a = 25 oc C 0.1 C a t a = 85 oc C C 1.6 a i li input leakage current on i/o pins v ss < v in < v dd C1 C 1 a input leakage current on wp and reset (when i/o2 and i/o3 functions disabled) C100 C 1 a i lo output leakage current v ss < v out < v dd C1 C 1 ? a v ih input high voltage 0.7 v dd Cv dd + 0.3 v v il input low voltag e C0.3 C 0.3 v dd v v oh1 output high voltage i oh = C1 ma, v dd = 2.7 v. 2.4 C C v v oh2 output high voltage i oh = C100 ? av dd C 0.2 C C v v ol1 output low voltage i ol = 2 ma, v dd = 2.7 v C C 0.4 v v ol2 output low voltage i ol = 150 ? aCC0.2v dc electrical c haracteristics (continued) over the operating range parameter description test conditions min typ [13] max unit
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 75 of 90 data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c 10 C years t a = 75 ? c38C t a = 65 ? c151C nv c endurance over operating temperature 10 14 C cycles capacitance parameter [14] description test conditions max unit c o output pin capacitance (so) t a = 25 c, f = 1 mhz, v dd = 3.0 v 6 pf c i input pin capacitance 5pf thermal resistance parameter [14] description test conditions 8-pin soic package 8-pin qfn package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 88.6 118 ? c/w ? jc thermal resistance (junction to case) 56 60 ? c/w note 14. this parameter is periodica lly sampled and n ot 100% tested.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 76 of 90 figure 104. ac test loads figure 105. ac timing input voltage reference levels ac test conditions parameter value cy15v104qsn CY15B104QSN input pulse levels (0 v to v dd ) 0 v to v dd 0 v to v dd input rise and fall times (10% to 90%) 1.8 ns 2.0 ns input timing refe rence voltages 0.3 v dd to 0.7 v dd 0.3 v dd to 0.7 v dd output timing reference voltages (v t ) v dd /2 v dd /2 load capacitance (c l ) 30 pf 30 pf 5pf v t =v dd /2 50 output all i/os in hi-z state 30 pf all i/os in output state except hi-z output 9 '' 9 9 '' 9 '' ,qsxwwlplqj uhihu hqfhohyhov ,qsxwohyhov
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 77 of 90 sdr ac switching characteristics parameters [15] description min max unit cypress parameter alt. parameter f sck C sck clock frequency 0 108 mhz t ch C clock high time 0.45 1/f sck C ns t cl C clock low time 0.45 1/f sck C ns t css t csu chip select (cs ) setup time 5 C ns t csh t csh chip select (cs ) hold time 4 C ns t hzcs t od [16, 17] output disable time C 6.5 ns t co output data valid time with 15-pf load (output driver set to 45 ?. over the operating range ) C 7 ns clock low to output valid C 15-pf load (output driver set to 45 ?. for v dd = 2.7 v to 3.6 v; over the operating range ) C 6.7 ns clock low to output valid C 30-pf load (output driver set to 45 ?. for v dd = 2.7 v to 3.6 v; over the operating range ) C 7 ns clock low to output valid C 30-pf load (output driver set to default 30 ?. over the operating range ) C 7 ns t oh C output hold time 1 C ns t cs [18] t d chip deselect (cs high) time before the command cycle in spi mode; all a ccesses (memory array and registers) 40 C ns chip deselect (cs high) time before the command cycle in dpi mode; all a ccesses except mem ory array access 110 C ns chip deselect (cs high) time before the command cycle in dpi mode (including d ual mode in extended spi); memory array access (non xip mode) 75 C ns chip deselect (cs high) time before the command cycle in dpi mode (including d ual mode in extended spi); memory array access (xip mode) 110 C ns chip deselect (cs high) time before the command cycle in qpi mode; all accesses e xcept memory array access 130 C ns chip deselect (cs high) time before the command cycle in qpi mode (including qua d mode in extended spi); memory array access (non xip mode) 110 C ns chip deselect (cs high) time before the command cycle in qpi mode (including qua d mode in extended spi); memory array access (xip mode) 130 C ns t sd t su data in setup time (with respect to sck) 2 C ns t hd t h data in hold time (with respect to sck) 3 C ns t clz clock low to output low-z 0 C ns t crcc crc calculation time (70 s + (0.8 s/byte of data)) 0.074 440 ms t crcs cs high to crc calculation suspends C 50 s t crcr cs high to crc calculation resumes C 50 s
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 78 of 90 figure 106. spi switching timing - single io, sdr figure 107. spi switching timing - multiple i/o, sdr figure 108. chip deselect (cs high) - t cs timing notes 15. these parameters are tested per ac test conditions on page 76 . 16. t od and t hz are specified with a load capacitance of 5 pf. transition is m easured when the outputs enter a high impedance state. 17. characterized but not 100% tested in production. 18. t cs is the minimum chip deselect (cs high) time before the new command cycle st arts in a specific s pi mode (spi, dpi or qpi). th is parameter ensures that previous operation is successfully complet ed before the host st arts a new command cycle. refer to figure 108 on page 78 . cs sck si t cs t csh t oh t hzcs t co t clz t hd t sd t css t ch t cl so valid data in data out hi-z hi-z x x x x cs sck io t cs t csh t oh t hzcs t co t clz t hd t sd t css t ch t cl valid data in data out x x x x cs sck i/os new command cycle t cs previous command cycle
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 79 of 90 figure 109. write protect setup and hold timing during write protect (wp ) timing parameters over the operating range parameters [19] description min max unit cypress parameter alt. parameter t wps t sw wp setup time (with respect to cs ) 20 C ns t wph t hw wp hold time (with respect to cs ) 20 C ns t wps 01234567 cs si sck 01234567 so 0000000 1 d7d6d5 d4d3d2d1d0 hi-z msb lsb opcode (01h) write data t wph reset (reset ) timing parameters over the operating range parameters [19] description min max unit cypress parameter alt. parameter t rs C hardware reset setup time 50 C ns t rph t rhsl , t rh hardware reset hold time 450 C s t rp t rlrh hardware reset pulse width 200 C ns t hreset hardware reset time C 450 s t sreset software reset time C 50 s t csl chip select (cs ) low time for jedec reset 500 C ns t csh_r chip select (cs ) high time fo r jedec reset 500 C ns t su si (i/o0) setup time (with respect to cs high) for jedec reset 5 C ns t hd_r si (i/o0) hold time (with respect to cs high) for jedec reset 5 C ns note 19. these parameters are tested per ac test conditions on page 76 .
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 80 of 90 figure 110. power cycle timing power cycle timing over the operating range parameter [20] description min max unit cypress parameter alt. parameter t pu power-up v dd (min) to fir st access (cs low) 450 C s t vr [ 21] v dd power-up ramp rate 30 C s/v t vf [21] v dd power-down ramp rate 20 C s/v t entdpd [22] t dp cs high to enter deep power-down (cs high to hibernate mode current) C 3 s t csdpd [22] cs pulse width to wake up from deep pow er-down mode 0.015 2.0 s t extdpd [23] t rdp recovery time from deep power-down mode (cs low to ready for access) C 10 s t enthib t hbn time to enter hibernate (cs high to hibernate mode current) C 3 s t exithib [24] t rec recovery time from hibernate mode (cs low to ready for access) C 450 s v dd (low) low v dd where initialization must occur 0.6 C v t pd v dd (low) time when v dd (low) at 0.6 v 130 C s v dd (low) time when v dd (low) at v ss 70 C v dd t vf t pu v dd (min) v dd (max) t vr v dd t pu v dd (min) v dd (max) t vr t pd v dd (low) no device access allowed device access allowed time time device access allowed notes 20. these parameters are tested per ac test conditions on page 76 . 21. slope measured at any point on the v dd waveform. 22. guaranteed by design. refer to figure 91 and figure 94 for deep sleep mode timing. 23. guaranteed by design. refer to figure 95 for hibernate mode timing. 24. characterized but not 100% tested in production.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 81 of 90 ordering code definitions ordering information ordering code device id package diagram package type operating range CY15B104QSN-108sxies 0000000006825150 001-85261 8-pin soic (eiaj) industrial all these parts are pb-free. cont act your local cypress sales r epresentative for availability of these parts. cy 15 b 104 qs - 108 s x i t options: blank = standard; t = tape and reel temperature range: i = industrial (- 40 c to + 85 c) x = pb-free package type: lp = 8-pin gqfn s = 8-pin soic (eiaj) frequency: 108 = 108 mhz cy = cypress 15 = f- ram voltage: v = 1. 71 v to 1. 89 v (1. 8 v typical) b = 1. 8 v to 3. 6 v (3. 0 v typical) density: 104 = 4- mbit interface: qs = quad spi f-ram n n = no inrush current control es = engineering sample;
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 82 of 90 package diagrams figure 111. 8-pin soic 208 mils package outline (001-85261) 001-85261 **
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 83 of 90 figure 112. 8-pin gqfn (3.23 3.28 0.55 mm) package outline (002-18131) a l1 0.45 0.50 dimensions b e d l e n symbol 0.25 min. 0.30 0.30 0.40 nom. 0.65 bsc 0.50 0.35 max. 8 1. all dimensions are in millimeters. notes: 0.35 0.45 0.55 0.55 3.18 3.23 3.28 3.23 3.28 3.33 a1 - 0.00 0.05 bottom view side view top view 002-18131 *c
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 84 of 90 acronyms document conventions units of measure acronym description cpha clock phase cpol clock polarity crc cyclic redundancy check dpi dual spi ecc error correction code eeprom electrically erasable programmable read-only memory eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mbit megabit mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond wohm % percent pf picofarad vvolt wwatt
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 85 of 90 document history page document title: CY15B104QSN/cy15 v104qsn, excelon?-ultra 4-mbit (512k 8) quad spi f-ram document number: 002-18293 rev. ecn no. orig. of change submission date description of change ** 5667997 zsk 03/22/2017 new data sheet. *a 5783777 zsk 06/23/2017 updated document title to read as cy15b1 04qsn/cy15v104qsn, 4-mbit (512k 8) quad spi f-ram. changed status from advance to preliminary. replaced cy15b104qs with CY15B104QSN in all instances across th e document. replaced cy15v104qs with cy15v104qsn in all instances across th e document. replaced cy15x104qs with cy15x104qsn in all instances across th e document. added 8-pin grid-array quad flat no-lead (gqfn) package details in all instances across the document. updated features : updated values under lo w-power consumption. updated logic block diagram . updated pinout : updated figure 1 , and figure 2 . updated pin definitions : updated details in description column corresponding to cs , wp / (i/o2) and reset / (i/o3) pins. updated functional overview : updated description. updated memory architecture : updated description. updated serial peripheral in terface (spi) bus : updated description; and also updated note 1 referred in table 1 . updated single channel spi (updated description). updated extended spi (updated description). updated terms used in spi protocol : updated chip select (cs) (updated description). updated data transmission (si/so) (updated figure 3 , and figure 4 ). updated most significant bit (msb) (updated description). updated mode bits (updated description). updated spi modes : updated double data rate (ddr) (updated description). updated power-up to first access : updated description ; and also updated table 2 . updated cy15x104qsn registers : updated status registers : updated status register 1 (sr1) (updated descripti on; and also updated ta b l e 3 , ta b l e 4 , and ta b l e 7 ). updated status register 2 (sr2) (updated descripti on; and also updated ta b l e 8 ). updated configuration registers : updated description. updated configuration register 1 (cr1) (updated description; and also updated ta b l e 1 0 , table 11 , ta b l e 1 2 , table latency (dummy) cycles for memory read commands - with xi p mode (ddr), and table 13 ). updated configuration register 2 (cr2) (updated description; and also updated ta b l e 1 4 , and ta b l e 1 5 ). updated configuration register 4 (cr4) (updated description; updated ta b l e 1 8 , and table 20 ; and also updated note 10 referred in table 20 ). updated configuration register 5 (cr5) (updated description; and also updated ta b l e 2 1 , and ta b l e 2 3 ). updated mode register (mr): updated description; and also upd ated table mode register (mr) details.
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 86 of 90 *a (cont.) 5783777 zsk 06/23/2017 updated functional description : updated command structure : updated description ; and also updated table 25 . updated write enable c ontrol commands (updated description). updated register access commands (updated description; and also updated ta b l e 3 1 ). updated memory write operation (updated description; updated table 32 , and ta b l e 3 3 ; and also updated fi gure ddr write (ddrwr ite) in qpi mode, figure 47 , and figure 49 , removed figures ddr write (ddrwrite) in spi mode, ddr write (ddrwrite) in dpi mode, ddr fast write (ddr_fast_w rite) in spi mode and ddr fast write (d dr_fast_write) in dpi mode). updated memory read operation (updated description; updated ta b l e 3 4 , and ta b l e 3 5 ; and also removed figures ddrf r in spi mode a nd ddrfr in dp i mode). updated special sector memory (updated description). updated error correction code (ecc) and cyclic redundancy check (updated description; updated table 40 , ta b l e 4 4 , and ta b l e 4 7 ; and also updated figure 70 , figure 71 , figure 72 , and figure crc calculation overflow). updated identification and serial number (updated figure 79 ). updated low power modes and resets (updated description; updated ta b l e 5 1 , and table 52 ; updated figure 91 , figure 95 , figure 101 , and figure 102 ; and also added figure 94 ). updated dc electrical characteristics : updated details corresponding to i sb , i dpd , and i li parameters. updated capacitance : updated details corresponding to c o , c i parameters. updated ac test conditions : updated figure 104 . updated sdr ac switching characteristics : updated details corresponding to t css , t csh , t co , and t hd parameters. removed t wps , t wph parameters and their details. updated ddr ac switch ing characteristics: updated details corresponding to t hzcs parameter. updated power cycle timing : updated details corresponding to t entdpd , t extdpd , t enthib , t exithib and t pd parameters. added t csdpd , v dd (low) parameters and thei r corresponding details. updated figure 110 . updated ordering information : updated part numbers. added a column device id and added details in that column. added a note below the table. *b 5891073 zsk 09/21/2017 updated functional overview : updated serial peripheral in terface (spi) bus : updated quad spi (qpi) (updated description). updated terms used in spi protocol : updated mode bits (updated description). updated wait states or dummy cycles (updated description). updated power-up to first access : updated ta b l e 2 . document history page (continued) document title: CY15B104QSN/cy15 v104qsn, excelon?-ultra 4-mbit (512k 8) quad spi f-ram document number: 002-18293 rev. ecn no. orig. of change submission date description of change
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 87 of 90 *b (cont.) 5891073 zsk 09/21/2017 updated cy15x104qsn registers : updated description. updated cy15x104qsn registers : updated configuration register 4 (cr4) (updated description; and also updated ta b l e 1 9 ). removed mode register (mr). updated functional description : updated command structure : updated description. added ta b l e 2 4 . updated ta b l e 2 5 . updated register access commands (updated description; and also updated ta b l e 3 1 ). updated error correction code (ecc) and cyclic redundancy check (updated description; updated ta b l e 4 5 , table 46 and table 47 ; updated figure 70 , figure 73 , and figure 76 and also removed figures read bus crc register (rbcrc) in spi mode, read bus crc register ( rbcrc) in dpi mode and read bu s crc register (rbcrc) in qpi mode). updated identification and serial number (updated description). updated low power modes and resets (updated description; updated figure 98 , figure 101 , and figure 102 ; removed figure jedec reset; added figure figure 103 ; and updated ta b l e 5 3 ). updated maximum ratings : updated details corresponding to maximum junction temperature . updated dc electrical characteristics : updated details corresponding to i dd1 , and i dd2 parameters. updated sdr ac switching characteristics : updated details corresponding to t cs parameter. added t crcc , t crcs , t crcr parameters and their details. updated note 18. added figure 108 . updated ddr ac switch ing characteristics: updated details corresponding to t cs parameter. added note t cs is the mini mum chip deselect (cs high) time before the new command cycle starts in a specif ic spi mode (spi or qpi). this parameter ensures that previous operation is succe ssfully completed before the ho st starts a new command cycle. refer t o figure 117 on page 81. and referred th e same note in t cs parameter. updated reset (reset) timing parameters : updated details in parameter and description columns for t rs , t rph , and t rp parameters. added t hreset , t sreset parameters and their details. updated package diagrams : spec 002-18131 C changed re vision from *a to *c. *c 5942580 zsk 10/24/2017 updated features : updated values under lo w-power consumption. updated functional overview : updated power-up to first access : updated description. updated sdr ac switching characteristics : updated details in description column corresponding to t cs parameter. updated ddr ac switch ing characteristics: updated details in description column corresponding to t cs parameter. updated ordering information : updated part numbers. updated ordering code definitions . document history page (continued) document title: CY15B104QSN/cy15 v104qsn, excelon?-ultra 4-mbit (512k 8) quad spi f-ram document number: 002-18293 rev. ecn no. orig. of change submission date description of change
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 88 of 90 *d 6044990 zsk 01/25/2018 updated document title to read as cy15b1 04qsn/cy15v104qsn, excelon?-ultra 4-mbit (5 12k 8) quad spi f-ram. updated features : updated details under single a nd multi i/o seri al peripheral i nterface (spi). updated values under lo w-power consumption. updated functional overview : updated spi modes : updated description. updated cy15x104qsn registers : updated status registers : updated status register 2 (sr2) (updated description). updated configuration registers : updated description. updated configuration register 1 (cr1) (updated table 10 ). updated functional description : updated command structure : updated memory write operation (updated description; updated table 32 , and ta b l e 3 3 ; and also updated fi gure ddr write (ddrwr ite) in qpi mode, a nd figure quad i/o write (qiow)). updated memory read operation (updated description; updated ta b l e 3 4 , and ta b l e 3 5 ; and also updated figur e ddrfr in qpi mode, figure 55 , and figure quad i/o read in ddr ( ddrqior) C in extended spi mode) . updated dc electrical characteristics : updated details corresponding to i dd1 , i dd2 , i dd3 , i sb , i dpd , and i hbn parameters. updated note 13. updated capacitance : updated details in test conditions column. updated sdr ac switching characteristics : updated details corresponding to t crcc parameter. updated ordering information : no change in part numbers. updated details in device id column. updated to new template. completing s unset review. *e 6085012 zsk 03/01/2018 removed double data rate (ddr) related information in all instances across the document. removed wrr command related inf ormation in all instances acro ss the document. updated pin definitions : updated details in description column corresponding to wp / (i/o2) pin. updated functional overview : updated spi modes : removed double data rate (ddr). updated cy15x104qsn registers : updated configuration registers : updated configuration register 1 (cr1) (removed table latency (dummy) cycles for memory read commands - with xip mode (ddr)). document history page (continued) document title: CY15B104QSN/cy15 v104qsn, excelon?-ultra 4-mbit (512k 8) quad spi f-ram document number: 002-18293 rev. ecn no. orig. of change submission date description of change
preliminary CY15B104QSN cy15v104qsn document number: 002-18293 rev. *e page 89 of 90 *e (cont.) 6085012 zsk 03/01/2018 updated functional description : updated command structure : updated register access commands (updated description; removed figures wrr in spi mode (wren not shown), wrr in dpi mode (wren not shown ) and wrr in qpi mode (wren not shown)). updated memory write operation (updated description; removed figures ddr write (ddrwrite) in qpi mode, d dr fast write ( ddr_fast_write) in qpi mode and quad i/o write (qiow)). updated memory read operation (updated description; updated table 35 ; removed figures ddrfr in qpi mode, quad i/o read in ddr (ddrqior) C in extended spi mode and quad i/o read in ddr (ddrqior) C in qpi mode). updated dc electrical characteristics : updated details corresponding to i dd3 parameter. removed ddr ac switching characteristics. document history page (continued) document title: CY15B104QSN/cy15 v104qsn, excelon?-ultra 4-mbit (512k 8) quad spi f-ram document number: 002-18293 rev. ecn no. orig. of change submission date description of change
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